UNISONIC TECHNOLOGIES CO., LTD
83CXXX
Preliminary
CMOS IC
4-PIN µP VOLTAGE MONITORS
WITH MANUAL RESET INPUT
DESCRIPTION
The UTC
83CXXX
is a microprocessor supervisory circuit. It has
an active-low RESET and push-pull outputs. The circuit can assert
a reset signal as long as the V
CC
power supplies voltage dropping
below a preset threshold and it keep the reset signal for at least
140ms when V
CC
has risen above the reset threshold. The reset
threshold can be operated with multi-supply voltages.
The UTC
83CXXX
provides the circuit with perfect reliability and
low cost through eliminating external components and adjustments
when applied with +5V, +3.3V, +3.0V power supply The UTC
83CXXX
also provide a de-bounced manual reset input.
The reset comparator can work despite of fast transients on
V
CC
, and the outputs are guaranteed to be in the right logic state
while V
CC
is down to 1V.
In applications, the UTC
83CXXX
is suitable for computers,
intelligent instruments, controllers, critical microprocessor and
microcomputer power monitors, portable or battery-powered
equipment, automotive.
FEATURES
* +3V, +3.3V, and +5V power-supply voltages
* Full temperature rated
* Supply current: 5µA
* Available in configuration: push-pull RESET output
* 140ms minimum power-on reset pulse width
* Guaranteed reset to V
CC
= +1V
* Power supply transient Immunity
* Eliminating external components
* Manual reset input
* Halogen Free
ORDERING INFORMATION
Ordering Number
Package
83CXXXG-AD4- R
SOT-143
Note: XXX: Output Voltage, refer to Marking Information.
83CXXXG-AD4-R
(1) Packing Type
(2) Package Type
(3) Halogen Free
(4) Output Voltage Code
(1) R: Tape Reel
(2) AD4: SOT-143
(3) G: Halogen Free
(4) XXX: Refer to Marking Information
Packing
Tape Reel
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QW-R502-353.a
83CXXX
MARKING INFORMATION
PACKAGE
VOLTAGE CODE
Preliminary
CMOS IC
MARKING
SOT-143
B: 2.93V
C: 3.08V
PIN CONFIGURATION
PIN DESCRIPTION
PIN NO
1
2
PIN NAME
GND
RESET
DESCRIPTION
Ground
RESET output remains low while V
CC
is below the reset threshold, and for at least
140ms after V
CC
rises above the reset threshold.
Manual reset input. A logic low on
MR asserts reset. Reset remains asserted as
long as MR is low and for at least 140ms after MR returns high, This active-low
input has an internal 20kΩ pull-up resistor. It can be driven from a TTL or
CMOS-logic line, or shorted to ground with a switch. Leave open if unused.
Supply voltage (+5V, +3.3V, +3.0V)
3
MR
4
V
CC
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83CXXX
PARAMETER
Terminal Voltage (respect to GND)
Push-Pull
RESET Voltage
Open Drain
Input Current
Preliminary
CMOS IC
ABSOLUTE MAXIMUM RATING
SYMBOL
V
CC
V
RESET
I
CC
RATINGS
-0.3 ~ +6.0
-0.3 ~ (V
CC
+0.3)
-0.3 ~ +6.0
20
20
I
OUT
Output Current ( RESET )
Power Dissipation (Ta =+70°C)
320
mW
P
D
Derated Above 70°C
4
mW/°C
Operating Temperature
T
OPR
-40~+105
°C
Storage Temperature Range
T
STG
-65~+150
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
UNIT
V
V
V
mA
mA
ELECTRICAL CHARACTERISTICS
(V
CC
= full range, Ta =-40°C~+105°C. Typical values are at Ta=25°C, unless otherwise specified)
83C293 (2.93V)
(V
CC
= 3.3V)
PARAMETER
SYMBOL
V
CC
V
IH
V
IL
V
TH
I
CC
I
OL
I
OH
V
CC
Range
MR Input Threshold
Reset Threshold
Supply Current
RESET Output Current
(push-pull active low)
Low
High
TEST CONDITIONS
Ta=0°C~+70°C
Ta=-40°C~+105°C
V
CC
>
V
TH(MAX)
Ta=25°C
V
CC
<
3.6V, Ta=-40°C~+105°C
V
CC
=2.5V,
V
RESET
= 0.5 V
V
CC
= 3.3V,
V
RESET
= 2.8 V
MIN
1.0
1.2
1.98
2.871
8
3
10
TYP
MAX
5.5
5.5
0.825
2.988
8
2.93
5
UNIT
V
V
V
V
V
μA
mA
mA
kΩ
ppm/°C
ms
μs
ns
μs
UNIT
V
V
V
V
V
μA
mA
mA
kΩ
ppm/°C
ms
μs
ns
μs
MR Pull-up Resistance
Reset Threshold Tempco
V
CC
to Reset Delay
Reset Active Timeout Period
MR Minima Pulse Width
MR Glitch Immunity (Note )
MR to Reset Propagation Delay
83C308 (3.08V)
(V
CC
=3.3V)
PARAMETER
V
CC
= V
TH
~(V
TH
-100mV)
V
CC
= V
TH(MAX)
t
MR
t
MD
SYMBOL
V
CC
V
IH
V
IL
V
TH
I
CC
I
OL
I
OH
TEST CONDITIONS
Ta=0°C~+70°C
Ta=-40°C~+105°C
V
CC
>
V
TH(MAX)
Ta=25°C
V
CC
<
3.6V, Ta=-40°C~+105°C
V
CC
=2.5V,
V
RESET
= 0.5 V
V
CC
= 3.3V,
V
RESET
= 2.8 V
140
20
70
15
310
10
100
0.5
TYP
30
520
V
CC
Range
MR Input Threshold
Reset Threshold
Supply Current
RESET Output Current
(push-pull active low)
Low
High
MIN
1.0
1.2
1.98
3.018
8
3
10
MAX
5.5
5.5
0.825
3.141
8
3.08
5
MR Pull-up Resistance
Reset Threshold Tempco
V
CC
to Reset Delay
V
CC
= V
TH
~ (V
TH
-100mV)
Reset Active Timeout Period
V
CC
= V
TH(MAX)
t
MR
MR Minima Pulse Width
MR Glitch Immunity (Note )
t
MD
MR to Reset Propagation Delay
Note: “Glitches” of 100ns or less typical values will not generate a reset pulse.
140
20
70
15
310
10
100
0.5
30
520
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83CXXX
DETAILED DESCRIPTION
Preliminary
CMOS IC
The UTC
83CXXX
have a push-pull output stage. A microprocessor’s (µP’s) reset input initiates the
microprocessor in a known state. The UTC
83CXXX
assert a reset signal as long as the V
CC
power supply voltage
drops below a preset threshold. When V
CC
has risen over the reset threshold, the devices keep the signal for at least
140ms. They have a function of preventing code-execution errors during power-up, power-down, or brownout
conditions by resetting.
See the manual reset input section if you want to see function that the manual reset input ( MR ) can initiate a
reset.
Manual Reset Input
Many products based on microprocessor need manual reset characteristic, allowing them to initiate a reset.
Reset keeps working while MR is low, and when MR returns high it is for the reset Active Timeout Period (t
RP
).
TTL or CMOS-logic levels, or with open-drain / collector outputs both can drive MR . MR will be started by a logic low
on manual reset .Because the input has a build-in 20kΩ pull-up resistor; it can be left open if it is not used. We can
put a 0.1µF capacitor from MR to ground if MR is driven from long cables or the device is used in a noisy
environment strengthening additional noise capacity. Connecting a normally open momentary switch from MR to
ground to create a manual-reset function, and external debounce circuitry is not required.
V
CC
UTC
83CXXX
RESET
R1=
100K
GND
Figure 1. RESET Valid to V
CC
= Ground Circuit
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83CXXX
Preliminary
CMOS IC
APPLICATION INFORMATION
1. Ensuring a Valid Reset Output Down to V
CC
= 0
The UTC
83CXXX
RESET output no more sinks current when V
CC
drops below 1V—it becomes an open
circuit. Therefore, high-impedance CMOS logic input connected to RESET can drift to undetermined voltages. This
presents no problem in most applications since most microprocessors and other circuitry can’t be operated when V
CC
is under 1V. In figure 1, however, in applications where RESET must be valid down to 0V. In order to causes any
stray leakage currents to flow to ground, adding a pull-down resistor to RESET , that holding RESET low. (R1’s
value is not critical and the value 100kΩ is large enough not to load RESET and small enough to pull RESET to
ground).
2. Benefits of Highly Accurate Reset Threshold
Most microprocessor supervisor ICs has reset threshold voltages between 5% and 10% below the value of
nominal supply voltages. If using ICs rated at only the nominal supply ±5%, this leaves an uncertainty zone where
the supply is between 5% and 10% low and where the reset may or may not be asserted.
The UTC 83C308 with high accuracy ensure that the reset is asserted closely to 5% limit and long before the
supply has declined to 10% below nominal.
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QW-R502-353.a
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