EPM7064SLC68-6 datasheet, PDF - EEWORLD Datasheet

EPM7064SLC68-6: DescriptionEE PLD, 6ns, 64-Cell, CMOS, PQCC68, PLASTIC, LCC-68; CategoryProgrammable logic devices Programmable logic; File Size2MB，82 Pages; ManufacturerAltera (Intel)

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EPM7064SLC68-6 Overview

EE PLD, 6ns, 64-Cell, CMOS, PQCC68, PLASTIC, LCC-68

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Altera (Intel)
Parts packaging code	LCC
package instruction	QCCJ, LDCC68,1.0SQ
Contacts	68
Reach Compliance Code	compliant
Other features	CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V
maximum clock frequency	151.5 MHz
In-system programmable	YES
JESD-30 code	S-PQCC-J68
JESD-609 code	e0
JTAG BST	NO
length	24.23 mm
Dedicated input times
Number of I/O lines	48
Number of macro cells	64
Number of terminals	68
Maximum operating temperature	70 °C
Minimum operating temperature
organize	0 DEDICATED INPUTS, 48 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	220
power supply	3.3/5,5 V
Programmable logic type	EE PLD
propagation delay	6 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	24.23 mm

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