EEWORLDEEWORLDEEWORLD

Part Number

Search

FTR-136-01-H-D

Description
Board Connector, 72 Contact(s), 2 Row(s), Male, Straight, Surface Mount Terminal,
CategoryThe connector    The connector   
File Size177KB,2 Pages
ManufacturerSAMTEC
Websitehttp://www.samtec.com/
Download Datasheet Parametric View All

FTR-136-01-H-D Overview

Board Connector, 72 Contact(s), 2 Row(s), Male, Straight, Surface Mount Terminal,

FTR-136-01-H-D Parametric

Parameter NameAttribute value
MakerSAMTEC
Reach Compliance Codecompliant
Connector typeBOARD CONNECTOR
Contact to complete cooperationGOLD
Contact completed and terminatedGOLD
Contact point genderMALE
Contact materialPHOSPHOR BRONZE
DIN complianceNO
Filter functionNO
IEC complianceNO
JESD-609 codee4
MIL complianceNO
Manufacturer's serial numberFTR
Mixed contactsNO
Installation methodSTRAIGHT
Installation typeBOARD
Number of rows loaded2
OptionsGENERAL PURPOSE
Terminal pitch1.27 mm
Termination typeSURFACE MOUNT
Total number of contacts72
MAC frame, program startup flow in flash memory
1. FrameRefer to "JN-AN-1001-Power-Estimation.pdf"All information operations in the 802.15.4 MAC layer are based on the symbol rate . When operating at 2.4-GHz, the symbol rate is defined as 62500 sym...
wateras1 RF/Wirelessly
How to generate executable files using LabVIEW
labview generates exe....
安_然 Test/Measurement
How to generate a process library-independent netlist from rtl code?
I am learning modelsim simulation and synopsys synthesis. Usually in synopsys we can use the following settings to generate netlist set SYNOPSYS_LIB /usr/synopsys/libraries/syn set target_library "$SY...
eeleader FPGA/CPLD
Ask a question about SIM3OO
The protector made of 430 MCU and SIM300 module uses SMS to control the device. Now there is a problem. When the protector is powered off, the device will not execute the command when it is turned on,...
wholefasten Embedded System
Communication between fpga and arm9!
What are the specific methods for communication between fpga and arm9? I hope friends who have done it before can give me some advice! Thank you!...
xiaoxin1 FPGA/CPLD
The hierarchical wordline structure can improve the SRAM read and write speed and reduce the circuit dynamic power consumption
The memory using hierarchical word line structure divides the entire storage array into several identical sub-arrays. Compared with the non-hierarchical word line structure, it requires multi-level wo...
是酒窝啊 Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 664  2521  891  2460  174  14  51  18  50  4 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号