FSTD16211 24-Bit Bus Switch with Level Shifting
June 2000
Revised April 2005
FSTD16211
24-Bit Bus Switch with Level Shifting
General Description
The Fairchild Switch FSTD16211 provides 24-bits of high-
speed CMOS TTL-compatible bus switching. The low On
Resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise. A diode to V
CC
has been
integrated into the circuit to allow for level shifting between
5V inputs and 3.3V outputs.
The device is organized as a 12-bit or 24-bit bus switch.
When OE
1
is LOW, the switch is ON and Port 1A is con-
nected to Port 1B. When OE
2
is LOW, Port 2A is connected
to Port 2B. When OE
1/2
is HIGH, a high impedance state
exists between the A and B Ports.
Features
s
4
:
switch connection between two ports
s
Voltage level shifting
s
Minimal propagation delay through the switch
s
Low l
CC
s
Zero bounce in flow-through mode
s
Control inputs compatible with TTL level
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number
FSTD16211G
(Note 1)(Note 2)
FSTD16211MTD
(Note 2)
Package Number
BGA54A
MTD56
Package Description
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1:
Ordering code “G” indicates Trays.
Note 2:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
© 2005 Fairchild Semiconductor Corporation
DS500313
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FSTD16211
Connection Diagrams
Pin Assignment for TSSOP
Pin Descriptions
Pin Name
OE
1
, OE
2
1A, 2A
1B, 2B
NC
Description
Bus Switch Enables
Bus A
Bus B
No Connect
Pin Assignment for FBGA
1
A
B
C
D
E
F
G
H
J
1A
2
1A
4
1A
6
1A
10
1A
12
2A
4
2A
6
2A
8
2A
12
2
1A
1
1A
3
1A
5
1A
9
1A
11
2A
3
2A
5
2A
7
2A
11
3
NC
1A
7
GND
1A
8
2A
1
2A
2
V
CC
2A
9
2A
10
4
OE
2
OE
1
1B
7
1B
8
2B
1
2B
2
GND
2B
9
2B
10
5
1B
1
1B
3
1B
5
1B
9
1B
11
2B
3
2B
5
2B
7
2B
11
6
1B
2
1B
4
1B
6
1B
10
1B
12
2B
4
2B
6
2B
8
2B
12
Truth Table
Inputs
OE
1
L
Pin Assignment for FBGA
L
H
H
OE
2
L
H
L
H
Inputs/Outputs
1A, 1B
1A
1A
Z
Z
1B
1B
2A
Z
2A, 2B
2A
Z
2B
2B
(Top Thru View)
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2
FSTD16211
Absolute Maximum Ratings
(Note 3)
Supply Voltage (V
CC
)
DC Switch Voltage (V
S
) (Note 4)
DC Input Control Pin Voltage (V
IN
)(Note 5)
DC Input Diode Current (l
IK
) V
IN
0V
DC Output (I
OUT
)
DC V
CC
/GND Current (I
CC
/I
GND
)
Storage Temperature Range (T
STG
)
0.5V to
7.0V
0.5V to
7.0V
0.5V to
7.0V
50 mA
128 mA
Recommended Operating
Conditions
(Note 6)
Power Supply Operating (V
CC)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
Input Rise and Fall Time (t
r
, t
f
)
Switch Control Input
Switch I/O
Free Air Operating Temperature (T
A
)
0 ns/V to 5 ns/V
0 ns/V to DC
-40
q
C to
85
q
C
4.5V to 5.5V
0V to 5.5V
0V to 5.5V
/
100 mA
65
q
C to
150
q
C
Note 3:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 4:
V
S
is the voltage observed/applied at either A or B Ports across the
switch.
Note 5:
The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 6:
Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
V
CC
Symbol
V
IK
V
IH
V
IL
V
OH
I
I
I
OZ
R
ON
Parameter
Clamp Diode Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level
Input Leakage Current
OFF-STATE Leakage Current
Switch On Resistance
(Note 8)
I
CC
Quiescent Supply Current
(V)
4.5
4.5–5.5
4.5–5.5
4.5–5.5
5.5
0
5.5
4.5
4.5
4.5
5.5
4
4
35
See Figure 3
2.0
0.8
T
A
Min
40
q
C to
85
q
C
Typ
(Note 7)
Max
Units
V
V
V
V
I
IN
Conditions
1.2
18 mA
r
1.0
10
P
A
P
A
P
A
:
:
:
mA
0
d
V
IN
d
5.5V
V
IN
V
IN
V
IN
V
IN
OE
1
V
IN
OE
1
V
IN
5.5V
0V, I
IN
0V, I
IN
2.4V, I
IN
OE
2
OE
2
64 mA
30 mA
15 mA
0
0
GND
V
CC
0
d
A, B
d
V
CC
r
1.0
7
7
50
1.5
10
V
CC
or GND, I
OUT
V
CC
or GND, I
OUT
P
A
mA
I
CCT
Increase in I
CC
per Control Input
5.0V and T
A
25
q
C
5.5
2.5
One Control Input at 3.4V
Other Control Inputs at V
CC
or GND
Note 7:
Typical values are at V
CC
Note 8:
Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the
voltages on the two (A or B) pins.
3
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FSTD16211
AC Electrical Characteristics
T
A
Symbol
Parameter
C
L
40
q
C to
85
q
C,
RD
500
:
Units
Conditions
Figure
Number
V
CC
4.5 – 5.5V
Max
0.25
ns
ns
ns
V
I
V
I
V
I
V
I
V
I
OPEN
7V for t
PZL
OPEN for t
PZH
7V for t
PLZ
OPEN for t
PHZ
Figures
1, 2
Figures
1, 2
Figures
1, 2
50pF, RU
Min
t
PHL
, t
PLH
t
PZH
, t
PZL
t
PHZ
, t
PLZ
Propagation Delay Bus to Bus (Note 9)
Output Enable Time
Output Disable Time
1.5
1.5
5.5
6.5
Note 9:
This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
Symbol
C
IN
C
I/O
Note 10:
T
A
(Note 10)
Parameter
Typ
3.5
5.5
Max
Units
pF
pF
V
CC
Conditions
5.0V
5.0V
Control Pin Input Capacitance
Input/Output Capacitance
25
q
C, f
V
CC
, OE
1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note:
Input driven by 50
:
source terminated in 50
:
Note:
CL includes load and stray capacitance
Note:
Input PRR
1.0 MHz, t
W
500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
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FSTD16211
Output Voltage HIGH vs. Supply Voltage
FIGURE 3.
5
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