TDPLD910-15 datasheet, PDF - EEWORLD Datasheet

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TDPLD910-15: DescriptionUV PLD, 18ns, PAL-Type, CMOS, CDIP40, CERDIP-40; CategoryProgrammable logic devices Programmable logic; File Size51KB，1 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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TDPLD910-15 Overview

UV PLD, 18ns, PAL-Type, CMOS, CDIP40, CERDIP-40

TDPLD910-15 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Intel
Parts packaging code	DIP
package instruction	DIP, DIP40,.6
Contacts	40
Reach Compliance Code	compliant
Other features	PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS
Architecture	PAL-TYPE
maximum clock frequency	45.4 MHz
JESD-30 code	R-GDIP-T40
JESD-609 code	e0
length	52.325 mm
Dedicated input times	12
Number of I/O lines	24
Number of entries	36
Output times	24
Number of product terms	240
Number of terminals	40
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	12 DEDICATED INPUTS, 24 I/O
Output function	MACROCELL
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP40,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	UV PLD
propagation delay	18 ns
Certification status	Not Qualified
Maximum seat height	5.72 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm

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TDPLD910-15 Related Products

	TDPLD910-15	TNPLD910-15
Description	UV PLD, 18ns, PAL-Type, CMOS, CDIP40, CERDIP-40	OT PLD, 18ns, PAL-Type, CMOS, PQCC44, PLASTIC, LCC-44
Is it Rohs certified?	incompatible	incompatible
Maker	Intel	Intel
Parts packaging code	DIP	LCC
package instruction	DIP, DIP40,.6	QCCJ, LDCC44,.7SQ
Contacts	40	44
Reach Compliance Code	compliant	compliant
Other features	PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS	PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS
Architecture	PAL-TYPE	PAL-TYPE
maximum clock frequency	45.4 MHz	45.4 MHz
JESD-30 code	R-GDIP-T40	S-PQCC-J44
JESD-609 code	e0	e0
length	52.325 mm	16.5862 mm
Dedicated input times	12	12
Number of I/O lines	24	24
Number of entries	36	36
Output times	24	24
Number of product terms	240	240
Number of terminals	40	44
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
organize	12 DEDICATED INPUTS, 24 I/O	12 DEDICATED INPUTS, 24 I/O
Output function	MACROCELL	MACROCELL
Package body material	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY
encapsulated code	DIP	QCCJ
Encapsulate equivalent code	DIP40,.6	LDCC44,.7SQ
Package shape	RECTANGULAR	SQUARE
Package form	IN-LINE	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	5 V
Programmable logic type	UV PLD	OT PLD
propagation delay	18 ns	18 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	5.72 mm	4.57 mm
Maximum supply voltage	5.25 V	5.25 V
Minimum supply voltage	4.75 V	4.75 V
Nominal supply voltage	5 V	5 V
surface mount	NO	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	J BEND
Terminal pitch	2.54 mm	1.27 mm
Terminal location	DUAL	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	15.24 mm	16.5862 mm

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