FSTD3306 2-Bit Low Power Bus Switch with Level Shifting
February 2001
Revised February 2001
FSTD3306
2-Bit Low Power Bus Switch with Level Shifting
General Description
The FSTD3306 is a 2-bit ultra high-speed CMOS FET bus
switch with enhanced level shifting circuitry and with TTL-
compatible active LOW control inputs. The low on resis-
tance of the switch allows inputs to be connected to out-
puts with minimal propagation delay and without
generating additional ground bounce noise. The device is
organized as a 2-bit switch with independent bus enable
(BE) controls. When BE is LOW, the switch is ON and Port
A is connected to Port B. When BE is HIGH, the switch is
OPEN and a high-impedance state exists between the two
ports. Reduced voltage drive to the gate of the FET switch
permits nominal level shifting of 5V to 3V through the
switch. Control inputs tolerate voltages up to 5.5V indepen-
dent of V
CC
.
Features
s
Typical 3
Ω
switch resistance at 5.0V V
CC
, V
IN
=
0V
s
Level shift facilitates 5V to 3.3V interfacing
s
Minimal propagation delay through the switch
s
Power down high impedance input/output
s
Zero bounce in flow through mode
s
TTL compatible active LOW control inputs
s
Control inputs are overvoltage tolerant
Ordering Code:
Order Number
FSTD3306MTC
Package Number
MTC08
Package Description
8-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagram
(Top View)
Pin Descriptions
Pin Name
A
B
BE
Description
Bus A Switch I/O
Bus B Switch I/O
Bus Enable Input
Function Table
Bus Enable Input (BE)
L
H
H
=
HIGH Logic Level
L
=
LOW Logic Level
Function
B Connected to A
Disconnected
© 2001 Fairchild Semiconductor Corporation
DS500480
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FSTD3306
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Switch Voltage (V
S
)
DC Output Voltage (V
IN
) (Note 2)
DC Input Diode Current
(I
IK
) V
IN
<
0V
DC Output (I
OUT
) Sink Current
DC V
CC
or Ground Current
(I
CC
/I
GND
)
Storage Temperature Range (T
STG
)
Junction Temperature
under Bias (T
J
)
Junction Lead Temperature (T
L
)
(Soldering, 10 Seconds)
Power Dissipation (P
D
) @
+
85
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
50 mA
128 mA
Recommended Operating
Conditions
(Note 3)
Supply Operating (V
CC
)
Control Input Voltage (V
IN
)
Switch Input Voltage (V
IN
)
Switch Output Voltage (V
OUT
)
Operating Temperature (T
A
)
Input Rise and Fall Time (t
r
, t
f
)
Control Input
Switch I/O
Thermal Resistance (
θ
JA
)
4.5V to 5.5V
0V to 5.5V
0V to 5.5V
0V to 5.5V
−
40
°
C to
+
85
°
C
0 ns/V to 5 ns
0 ns/V to DC
250
°
C/W
±
100 mA
−
65
°
C to
+
150
°
C
+
150
°
C
+
260
°
C
250 mW
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 3:
Unused logic inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
V
OH
I
IN
I
OFF
R
ON
Parameter
Clamp Diode Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
Input Leakage Current
Power OFF Leakage Current
Switch On Resistance
(Note 4)
I
CC
Quiescent Supply Current
V
CC
(V)
4.5
4.5–5.5
4.5–5.5
4.5–5.5
5.5
5.5
4.5
4.5
4.5
5.5
1.1
∆
I
CC
Increase in I
CC
per Input
(Note 5)
1.5
10
5.5
1
2.5
mA
µA
mA
3
3
15
see Figure 3
±1.0
±1.0
7
7
50
Ω
2.0
0.8
Min
T
A
= −40°C
to
+85°C
Typ
Max
−1.2
Units
V
V
V
V
µA
µA
V
IN
=
V
CC
0
≤
V
IN
≤
5.5V
0
≤
A, B
≤
V
CC
V
IN
=
0V, I
IN
=
64 mA
V
IN
=
0V, I
IN
=
30 mA
V
IN
=
2.4V, I
IN
=
15 mA
V
IN
=
V
CC
or GND, I
OUT
=
0
BE
1
=
BE
2
=
GND
BE
1
=
BE
2
=
V
CC
V
IN
=
3.4V, I
O
=
0, one Control
Input Only, Other BE
=
V
CC
Conditions
I
IN
= −18
mA
Note 4:
Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
Note 5:
Per TTL driven input (V
IN
=
3.4V, control input only). A and B pins do not contribute to I
CC
.
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2
FSTD3306
AC Electrical Characteristics
T
A
= −40°C
to
+85°C,
Symbol
t
PHL
,
t
PLH
t
PZL
,
t
PZH
t
PLZ
,
t
PHZ
Output Disable Time
4.5–5.5
0.8
3.5
4.8
ns
Parameter
Prop Delay Bus to Bus
(Note 6)
Output Enable Time
4.5–5.5
1.0
3.5
5.8
ns
V
I
=
7V for t
PZL
V
I
=
0V for t
PZH
V
I
=
7V for t
PLZ
V
I
=
0V for t
PHZ
V
CC
(V)
4.5–5.5
C
L
=
50 pF, RU
=
RD
=
500Ω
Min
Typ
Max
0.25
ns
V
I
=
OPEN
Figures
1, 2
Figures
1, 2
Figures
1, 2
Units
Conditions
Figure
Number
Note 6:
This parameter is guaranteed. The bus switch contributes no propagation delay other than the RC delay of the typical On resistance of the switch
and the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance). The specified limit is calculated on this basis.
Capacitance
Symbol
C
IN
C
I/O
(OFF)
C
I/O
(ON)
Parameter
Control Pin Input Capacitance
Port OFF Capacitance
Port ON Capacitance
Typ
2.5
6
12
Max
Units
pF
pF
pF
V
CC
=
0V
V
CC
=
5.0V
=
BE
V
CC
=
5.0V, BE
=
0V
Conditions
AC Loading and Waveforms
Input driven by 50Ω source terminated in 50Ω
C
L
includes load and stray capacitance
Input PRR
=
1.0 MHz; t
W
=
500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
3
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FSTD3306
DC Characteristics
FIGURE 3. Typical High Level Output Voltage vs. Supply Voltage
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4
FSTD3306 2-Bit Low Power Bus Switch with Level Shifting
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC08
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
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to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
5
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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