S E M I C O N D U C T O R
CD74FCT16952T,
CD74FCT162952T
Fast CMOS 16-Bit Registered Transceiver
Ordering Information
TEMP.
RANGE
(
o
C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
PKG.
NO.
December 1996
Features
• Advanced 0.6 micron CMOS Technology
• These Devices Are High-speed, Low Power Devices
with High Current Drive
• V
CC
= 5V
±10%
• Hysteresis on All Inputs
• CD74FCT16952T
- High Output Drive: I
OH
= -32mA; I
OL
= 64mA
- Power Off Disable Outputs Permit “Live Insertion”
- Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25
o
C
• CD74FCT162952T
- Balanced Output Drivers:
±24mA
- Reduced System Switching Noise
- Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V, T
A
= 25
o
C
PART NUMBER
CD74FCT16952ATMT
CD74FCT16952ATSM
CD74FCT16952TMT
CD74FCT16952TSM
CD74FCT16952CTMT
CD74FCT16952CTSM
CD74FCT16952DTMT
CD74FCT16952DTSM
CD74FCT16952ETMT
CD74FCT16952ETSM
CD74FCT162952ATMT
CD74FCT162952ATSM
CD74FCT162952TMT
CD74FCT162952TSM
CD74FCT162952CTMT
CD74FCT162952CTSM
CD74FCT162952DTMT
CD74FCT162952DTSM
CD74FCT162952ETMT
CD74FCT162952ETSM
PACKAGE
56 Ld TSSOP M56.240-P
56 Ld SSOP
M56.300-P
56 Ld TSSOP M56.240-P
56 Ld SSOP
M56.300-P
56 Ld TSSOP M56.240-P
56 Ld SSOP
M56.300-P
56 Ld TSSOP M56.240-P
56 Ld SSOP
M56.300-P
56 Ld TSSOP M56.240-P
56 Ld SSOP
M56.300-P
Description
These devices are 16-bit registered transceivers organized
with two sets of eight D-type latches with separate input and
output controls for each set. For data flow from A-to-B, for
example, the A-to-B Enable (
X
CEAB) input must be LOW in
order to enter data from
X
A
X
. The data present on the A port
will be clocked on the B register when
X
CLKAB toggles from
LOW-to-HIGH. The
X
OEAB control performs the output
enable function on the B port. Control of data from B-to-A is
similar, but uses the
X
CEBA, xCLKBA, and
X
OEBA inputs.
By connecting the control pins of the two independent trans-
ceivers together, a full 16-bit operation can be achieved. The
output buffers are designed with a Power-Off disable allow-
ing “live insertion” of boards when used as backplane drivers.
The CD74FCT16952T output buffers are designed with a
Power-Off disable allowing “live insertion” of boards when
used as backplane drivers.
The CD74FCT162952T has
±24mA
balanced output drivers.
It is designed with current limiting resistors at its outputs to
control the output edge rate resulting in lower ground bounce
and undershoot. This eliminates the need for external termi-
nating resistors for most interface applications.
56 Ld TSSOP M56.240-P
56 Ld SSOP
M56.300-P
56 Ld TSSOP M56.240-P
56 Ld SSOP
M56.300-P
56 Ld TSSOP M56.240-P
56 Ld SSOP
M56.300-P
56 Ld TSSOP M56.240-P
56 Ld SSOP
M56.300-P
56 Ld TSSOP M56.240-P
56 Ld SSOP
M56.300-P
NOTE: When ordering, use the entire part number. Add the suffix 96
to obtain the variant in the tape and reel.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
Harris Corporation 1996
File Number
4191.1
1
CD74FCT16952T, CD74FCT162952T
Pinout
CD74FCT16952T, CD74FCT162952T
(SSOP, TSSOP)
TOP VIEW
1
OEAB
1
CLKAB
1
CEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OEBA
1
CLKBA
1
CEBA
GND
1
A
0
1
A
1
GND
1
B
0
1
B
1
V
CC
1
A
2
1
A
3
1
A
4
V
CC
1
B
2
1
B
3
1
B
4
GND
1
A
5
1
A
6
1
A
7
2
A
0
2
A
1
2
A
2
GND
1
B
5
1
B
6
1
B
7
2
B
0
2
B
1
2
B
2
GND
2
A
3
2
A
4
2
A
5
GND
2
B
3
2
B
4
2
B
5
V
CC
2
A
6
2
A
7
V
CC
2
B
6
2
B
7
GND
2
CEAB
2
CLKAB
2
OEAB
GND
2
CEBA
2
CLKBA
2
OEBA
2
CD74FCT16952T, CD74FCT162952T
Functional Block Diagram
1
OEBA
1
CEBA
2
OEBA
2
CEBA
1
CLKBA
1
OEAB
1
CEAB
2
CLKBA
2
OEAB
2
CEAB
1
CLKAB
2
CLKAB
1
A
0
D
C
1
B
0
2
A
0
D
C
2
B
0
D
C
D
C
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
TRUTH TABLE
(NOTES 1, 2)
INPUTS
X
CEAB
X
CLKAB
OUTPUTS
XOEAB
L
L
L
L
H
X
A
X
X
B
X
H
X
L
L
X
NOTES:
X
L
↑
↑
X
X
X
L
H
X
B (Note 3)
B (Note 3)
L
H
High Z
1. H = High Voltage Level
L = Low Voltage Level
X = Don't Care or Irrelevant
↑
= LOW-to-HIGH Transition
Z = High Impedance
2. A-to-B data flow shown. B-to-A flow control is the same, except using
X
CEBA,
X
CLKBA, and
X
OEBA.
3. Level of B before the indicated steady-state input conditions were established.
3
CD74FCT16952T, CD74FCT162952T
Pin Descriptions
PIN NAME
X
OEAB
DESCRIPTION
A-to-B Output Enable Input
(Active LOW)
B-to-A Output Enable Input
(Active LOW)
A-to-B Clock Enable Input (Active LOW)
B-to-A Clock Enable Input (Active LOW)
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A
Three-State Outputs (Note 4)
B-to-A Data Inputs or A-to-B
Three-State Outputs (Note 4)
Ground
Power
X
OEBA
X
CEAB
X
CEBA
X
CLKAB
X
CLKBA
X
A
X
X
B
X
GND
V
CC
4
CD74FCT16952T, CD74FCT162952T
Absolute Maximum Ratings
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120mA
Thermal Information
Thermal Resistance (Typical, Note 4)
θ
JA
(
o
C/W)
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
(Lead Tips Only)
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Supply Voltage to Ground Potential
Inputs and V
CC
Only. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
Supply Voltage to Ground Potential
Outputs and D/O Only. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.0V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
4.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETERS
SYMBOL
(NOTE 5)
TEST CONDITIONS
MIN
(NOTE 6)
TYP
MAX
UNITS
DC ELECTRICAL SPECIFICATIONS
Over the Operating Range, T
A
= -40
o
C to 85
o
C, V
CC
= 5.0V
±10%
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input HIGH Current
Input HIGH Current
V
IH
V
IL
I
IH
I
IH
I
IH
I
IH
I
IL
I
IL
I
IL
I
IL
I
BHH
I
BHL
High Impedance Out-
put Current (Three-
State) (Note 10)
Clamp Diode Voltage
Short Circuit Current
Output Drive Current
Input Hysteresis
I
OZH
I
OZL
V
IK
I
OS
I
O
V
H
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Standard Input, V
CC
= Max
Standard I/O, V
CC
= Max
Bus Hold Input (Note 8)
V
CC
= Max
Bus Hold I/O (Note 8)
V
CC
= Max
Standard Input, V
CC
= Min
Standard I/O, V
CC
= Min
Bus Hold Input (Note 8)
V
CC
= Min
Bus Hold I/O (Note 8)
V
CC
= Min
Bus Hold Input (Note 8)
V
CC
= Min
V
CC
= Max
V
CC
= Max
V
CC
= Min, I
IN
= -18mA
V
CC
= Max (Note 7), V
OUT
= GND
V
CC
= Max (Note 7), V
OUT
= 2.5V
V
IN
= V
CC
V
IN
= V
CC
V
IN
= V
CC
V
IN
= V
CC
V
IN
= GND
V
IN
= GND
V
IN
= GND
V
IN
= GND
V
IN
= 2.0V
V
IN
= 0.8V
V
OUT
= 2.7V
V
OUT
= 0.5V
2.0
-
-
-
-
-
-
-
-
-
-
0.8
1
1
±100
±100
-1
-1
±100
±100
-
-
1
-1
-1.2
-200
-180
-
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
V
mA
mA
mV
Input HIGH Current
-
-
Input LOW Current
Input LOW Current
Input LOW Current
-
-
-
-
-
-
Input LOW Current
-
-
Bus Hold
Sustain Current
-50
50
-
-
-
-80
-50
-
-
-
-
-
-0.7
-140
-
100
5
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