Low Skew, 1-to-6, Crystal/ LVCMOS/
Differential-to-3.3V, 2.5V LVPECL Fanout Buffer
ICS8536-01
DATA SHEET
G
ENERAL
D
ESCRIPTION
The ICS8536-01 is a low skew, high performance 1-to-6
Selectable Crystal, Single-Ended, or Differential Input-to-
3.3V, 2.5V LVPECL Fanout Buffer. The ICS8536-01 has
selectable crystal, single ended or differential clock inputs.
The single ended clock input accepts LVCMOS or LVTTL
input levels and translates them to LVPECL levels. The
CLK1, nCLK1 pair can accept most standard differential
input levels. The output enable is internally synchronized to
eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8536-01 ideal for those applications demanding
well defined performance and repeatability.
F
EATURES
• Six 3.3V, 2.5V LVPECL outputs
• Selectable crystal oscillator, differential CLK1, nCLK1 pair
or LVCMOS/LVTTL clock input
• CLK1, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
• Crystal frequency range: 12MHz - 40MHz
•
Output skew: 55ps (maximum) CLK1, nCLK1 @ 3.3V
•
Part-to-part skew: 450ps (maximum)
•
Additive phase jitter, RMS: 0.19ps (typical)
• Full 3.3V or 2.5V supply mode
• 0°C to 70°C ambient operating temperature
•
Available in lead-free (RoHS 6) packages
B
LOCK
D
IAGRAM
CLK_EN
Pullup
D
Q
CLK_SEL0
Pulldown
CLK_SEL1
Pulldown
LE
P
IN
A
SSIGNMENT
nQ2
Q2
V
CC
nQ1
Q1
V
EE
nQ0
Q0
CLK_SEL0
XTAL_IN
XTAL_OUT
CLK_EN
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q3
nQ3
V
CC
Q4
nQ4
V
CC
Q5
nQ5
CLK_SEL1
nCLK1
CLK1
CLK0
XTAL_IN
Q0
OSC
XTAL_OUT
CLK0
Pulldown
CLK1
Pulldown
nCLK1
Pullup
00
nQ0
6 LVPECL Outputs
01
ICS8536-01
Q5
nQ5
1X
24-Lead TSSOP
4.40mm x 7.8mm x 0.925mm
package body
G Package
Top View
ICS8536-01 REVISION B AUGUST 17, 2012
1
©2012
Integrated Device Technology, Inc.
ICS8536-01 Data Sheet
CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 19, 22
4, 5
6
7, 8
9, 16
10, 11
12
13
14
15
17, 18
20, 21
23, 24
Name
nQ2, Q2
V
CC
nQ1, Q1
V
EE
nQ0, Q0
CLK_SEL0,
CLK_SEL1
XTAL_IN,
XTAL_OUT
CLK_EN
CLK0
CLK1
nCLK1
nQ5, Q5
nQ4, Q4
nQ3, Q3
Type
Output
Power
Output
Power
Ouput
Input
Input
Input
Input
Input
Input
Output
Output
Output
Description
Differential output pair. LVPECL interface levels.
Power supply pins.
Differential output pair. LVPECL interface levels.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Pulldown Clock select pins. LVCMOS/LVTTL interface levels. See Table 3B.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
Pullup
When LOW, the outputs are disabled.
LVCMOS / LVTTL interface levels. See Table 3A.
Pulldown LVCMOS/LVTTL clock input.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pulup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
ICS8536AG-01 REVISION B AUGUST 17, 2012
2
©2012
Integrated Device Technology, Inc.
ICS8536-01 Data Sheet
CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_EN
0
0
0
1
1
CLK_SEL1
0
0
1
0
0
CLK_SEL0
0
1
X
0
1
Selected Source
XTAL
CLK0
CLK1, nCLK1
XTAL
CLK0
Q0:Q5
Disabled
Disabled
Disabled
Enabled
Enabled
Outputs
nQ0:nQ5
Disabled
Disabled
Disabled
Enabled
Enabled
1
1
X
CLK1, nCLK1
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as show in
Figure 1.
In the active mode, the state of the outputs are a function of the selected clock input as described in Table 3B.
Disabled
nCLK1
CLK0, CLK1,
XTAL
CLK_EN
Enabled
nQ0:nQ5
Q0:Q5
F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
ICS8536AG-01 REVISION B AUGUST 17, 2012
3
©2012
Integrated Device Technology, Inc.
ICS8536-01 Data Sheet
CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
84.6°C/W (0 mps)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V = 0V, T
A
= 0°C
TO
70°C
EE
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
85
Units
V
mA
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
85
Units
V
mA
T
ABLE
4C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%
OR
2.5V±5%, V = 0V, T
A
= 0°C
TO
70°C
EE
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
CLK0,
CLK_SEL0:1
CLK_EN
CLK0,
CLK_SEL0:1
CLK_EN
Test Conditions
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
Minimum Typical
2
1. 7
-0.3
-0.3
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.7
150
5
Units
V
V
V
V
µA
µA
µA
µA
I
IL
-5
-150
ICS8536AG-01 REVISION B AUGUST 17, 2012
4
©2012
Integrated Device Technology, Inc.
ICS8536-01 Data Sheet
CRYSTAL/LVCMOS/DIFFERENTIAL-TO-LVPECL FANOUT BUFFER
T
ABLE
4D. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%
OR
2.5V±5%, V = 0V, T
A
= 0°C
TO
70°C
EE
Symbol
I
IH
I
IL
Parameter
Input High Current
Input Low Current
nCLK1
CLK1
nCLK1
Test Conditions
V
CC
= V
IN
= 3.465V or 2.625V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V or 2.625V, V
IN
= 0V
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
-150
-5
0.15
V
EE
+ 0.5
1.3
V
CC
- 0.85
CLK1
V
CC
= 3.465V or 2.625V, V
IN
= 0V
Peak-to-Peak Input Voltage;
V
PP
NOTE 1
Common Mode Input Voltage;
V
CMR
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
V
V
T
ABLE
4E. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V = 0V, T
A
= 0°C
TO
70°C
EE
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
4F. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V±5%, V = 0V, T
A
= 0°C
TO
70°C
EE
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.4
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.5
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
12
Test Conditions
Minimum
Typical Maximum
40
50
7
1
Units
MHz
Ω
pF
mW
Fundamental
ICS8536AG-01 REVISION B AUGUST 17, 2012
5
©2012
Integrated Device Technology, Inc.
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