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935300049118

Description
Serial In Parallel Out, HC/UH Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16
Categorylogic    logic   
File Size158KB,21 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
Download Datasheet Parametric View All

935300049118 Overview

Serial In Parallel Out, HC/UH Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16

935300049118 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNexperia
package instructionTSSOP,
Reach Compliance Codecompliant
Counting directionRIGHT
seriesHC/UH
JESD-30 codeR-PDSO-G16
JESD-609 codee4
length5 mm
Logic integrated circuit typeSERIAL IN PARALLEL OUT
Humidity sensitivity level1
Number of digits8
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)295 ns
Filter levelAEC-Q100
Maximum seat height1.1 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceNickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
Trigger typePOSITIVE EDGE
width4.4 mm
minfmax20 MHz
74HC4094-Q100; 74HCT4094-Q100
8-stage shift-and-store bus register
Rev. 1 — 30 January 2013
Product data sheet
1. General description
The 74HC4094-Q100; 74HCT4094-Q100 is an 8-bit serial-in/serial or parallel-out shift
register with a storage register and 3-state outputs. Both the shift and storage register
have separate clocks. The device features a serial input (D) and two serial outputs (QS1
and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP
input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow
cascading when clock edges are fast. The same data is available at QS2 on the next
HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow.
The data in the shift register is transferred to the storage register when the STR input is
HIGH. Data in the storage register appears at the outputs whenever the output enable
input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance
OFF-state. Operation of the OE input does not affect the state of the registers. Inputs
include clamp diodes that enable the use of current limiting resistors to interface inputs to
voltages in excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Complies with JEDEC standard JESD7A
Input levels:
For 74HC4094-Q100: CMOS level
For 74HCT4094-Q100: TTL level
Low-power dissipation
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
3. Applications
Serial-to-parallel data conversion
Remote control holding register
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