A
PPLICATION
N
OTE
A V A I L A B L E
AN20 • AN42–48 • AN50-53 • AN73 • AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Power/2-Wire Serial Bus
X9241
Quad Digitally Controlled Potentiometer (XDCP
™
)
FEATURES
• Four potentiometers in one package
• 2-wire serial interface
• Register oriented format
—Direct read/write/transfer of wiper positions
—Store as many as four positions per
potentiometer
• Terminal Voltages: ±5V
• Cascade resistor arrays
• Low power CMOS
• High Reliability
—Endurance–100,000 data changes per bit per
register
—Register data retention–100 years
• 16-bytes of nonvolatile memory
• 3 resistor array values
—2K
Ω
to 50K
Ω
mask programmable
—Cascadable for values of 500
Ω
to 200K
Ω
• Resolution: 64 taps each pot
• 20-lead plastic DIP, 20-lead TSSOP and 20-lead
SOIC packages
DESCRIPTION
The X9241 integrates four digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
V
CC
V
SS
R0 R1
Wiper
Counter
Register
(WCR)
V
H0
/R
H0
R0 R1
Wiper
Counter
Register
(WCR)
Register
Array
Pot 2
V
H2
/
R
H2
V
L2
/R
L2
V
W2
/R
W2
R2 R3
SCL
SDA
A0
A1
A2
A3
V
L0
/R
L0
V
W0
/R
W0
R2 R3
Interface
and
Control
Circuitry
Data
8
R0 R1
Wiper
Counter
Register
(WCR)
Register
Array
Pot 1
V
H1
/R
H1
R0 R1
Wiper
Counter
Register
(WCR)
Register
Array
Pot 3
V
H3
/R
H3
R2 R3
V
L1
/R
L1
V
W1
/R
W1
R2 R3
V
L3
/R
L3
V
W3
/R
W3
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1 of 18
X9241
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9241.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical
values, refer to the guidelines for calculating typical
values on the bus pull-up resistors graph.
Address
The Address inputs are used to set the least
significant 4 bits of the 8-bit slave address. A match in
the slave address serial data stream must be made
with the Address input in order to initiate
communication with the X9241.
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
—V
H3
/R
H3
), V
L
/R
L
(V
L0
/R
L0
—V
L3
/R
L3
)
The R
H
and R
L
inputs are equivalent to the terminal
connections on either end of a mechanical
potentiometer.
V
W
/R
W
(V
W0
/R
W0
—V
W3
/R
W3
)
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
V
W0
/R
W0
V
L0
/R
L0
V
H0
/R
H0
A0
A2
V
W1
/R
W1
V
L1
/R
L1
VH1
SDA
V
SS
PIN CONFIGURATION
DIP/SOIC/TSSOP
1
2
3
4
5
6
7
8
9
10
X9241
20
19
18
17
16
15
14
13
12
11
V
CC
V
W3
/R
W3
V
L3
/R
L3
V
H3
/R
L3
A1
A3
SCL
V
W2
/R
W2
V
L2
/R
L2
V
H2
/R
H2
PIN NAMES
Symbol
SCL
SDA
A0–A3
V
H0
/R
H0
–V
H3
/R
H3
,
V
L0
/R
L0
–V
L3
/R
L3
V
W0
/R
W0
–V
W3
/R
W3
Description
Serial Clock
Serial Data
Address
Potentiometer Pins
(terminal equivalent)
Potentiometers Pins
(wiper equivalent)
PRINCIPLES OF OPERATION
The X9241 is a highly integrated microcircuit
incorporating four resistor arrays, their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
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X9241
Serial Interface
The X9241 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9241 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t
LOW
). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9241 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
HIGH
). The X9241 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this
condition is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW
to acknowledge that it successfully received the eight
bits of data. See Figure 7.
The X9241 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the
command byte. If the command is followed by a data
byte the X9241 will respond with a final acknowledge.
Array Description
The X9241 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor
segment is a FET switch connected to the wiper (V
W
/
R
W
) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six least significant bits of the WCR are decoded to
select, and enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers
and the WCR can be read and written by the host
system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier (refer to Figure 1 below). For the X9241
this is fixed as 0101[B].
Figure 1. Slave Address
Device Type
Identifier
0
1
0
1
A3
A2
A1
A0
Device Address
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0-A3 inputs. The X9241 compares the
serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9241 to respond with an acknowledge.
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3 of 18
X9241
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle
time. Once the stop condition is issued to indicate the
end of the nonvolatile write command the X9241
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the device slave address. If the
X9241 is still busy with the write operation no ACK will
be returned. If the X9241 has completed the write
operation an ACK will be returned and the master can
then proceed with the next operation.
Flow 1. ACK Polling Sequence
Instructions
Nonvolatile Write
Command Completed
Enter ACK Polling
Register
Select
Instruction Structure
The next byte sent to the X9241 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of four pots and when applicable they
point to one of four associated registers. The format is
shown below in Figure 2.
Figure 2. Instruction Byte Format
Potentiometer
Select
I3
I2
I1
I0
P1
P0
R1
R0
Issue
START
The four high order bits define the instruction. The next
two bits (P1 and P0) select which one of the four
potentiometers is to be affected by the instruction. The
last two bits (R1 and R0) select one of the four
registers that is to be acted upon when a register
oriented instruction is issued.
Issue STOP
Issue Slave
Address
ACK
Returned?
Yes
No
FurTher
OperaTion?
Yes
Issue
Instruction
No
Issue STOP
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is
illustrated in Figure 3. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM. The response of
the wiper to this action will be delayed t
STPWV
. A
transfer from WCR current wiper position, to a Data
Register is a write to nonvolatile memory and takes a
minimum of t
WR
to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein
the transfer occurs between all four of the
potentiometers and one of their associated registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9241; either between the host and
one of the Data Registers or directly between the host
and the WCR. These instructions are: Read WCR,
read the current wiper position of the selected pot;
Write WCR, change current wiper position of the
selected pot; Read Data Register, read the contents of
the selected nonvolatile register; Write Data Register,
write a new value to the selected Data Register. The
sequence of operations is shown in Figure 4.
Proceed
Proceed
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X9241
The Increment/Decrement command is different from
the other commands. Once the command is issued and
the X9241 has responded with an acknowledge, the
master can clock the selected wiper up and/or down in
one segment steps; thereby, providing a fine tuning
capability to the host. For each SCL clock pulse (t
HIGH
)
while SDA is HIGH, the selected wiper will move one
Figure 3. Two-Byte Instruction Sequence
SCL
resistor segment towards the V
H
/R
H
terminal. Similarly,
for each SCL clock pulse while SDA is LOW, the
selected wiper will move one resistor segment towards
the V
L
/R
L
terminal. A detailed illustration of the
sequence and timing for this operation are shown in
Figures 5 and 6 respectively.
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
P1 P0
R1 R0
A
C
K
S
T
O
P
Figure 4. Three-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0 A
C
K
I3
I2
I1 I0
P1 P0 R1 R0
A CM DW D5 D4 D3 D2 D1 D0 A
C
C
K
K
S
T
O
P
Figure 5. Increment/Decrement Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1
I0
X
X
P1 P0 R1 R0
A
C
K
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
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Characteristics subject to change without notice.
5 of 18
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