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Datasheet> All Categories > logic> logic> IDT74FCT163373CPA8
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IDT74FCT163373CPA8

Description
Bus Driver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, TSSOP-48
Categorylogic    logic   
File Size71KB，7 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT74FCT163373CPA8 Overview

Bus Driver, FCT Series, 2-Func, 8-Bit, True Output, CMOS, PDSO48, TSSOP-48

IDT74FCT163373CPA8 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP-48
Contacts48
Reach Compliance Codenot_compliant
Other featuresMAX O/P SKEW = 0.5NS; TYP VOLP = 0.3V
seriesFCT
JESD-30 codeR-PDSO-G48
JESD-609 codee0
length12.5 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of digits8
Number of functions2
Number of ports2
Number of terminals48
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP48,.3,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)240
power supply3/3.3 V
Prop。Delay @ Nom-Sup4.2 ns
propagation delay (tpd)5.5 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperature20
width6.1 mm

IDT74FCT163373CPA8 Preview

IDT74FCT163373A/C
3.3V CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT
TRANSPARENT LATCH
IDT74FCT163373A/C
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range, or V
CC
= 2.7V to 3.6V, Extended
Range
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V components
• Available in SSOP and TSSOP packages
FEATURES:
DESCRIPTION:
The FCT163373 16-bit transparent D-type latches are built using
advanced dual metal CMOS technology. These high-speed, low-power
latches are ideal for temporary storage of data. They can be used for
implementing memory address latches, I/O ports, and bus drivers. The
Output Enable and Latch Enable controls are organized to operate each
device as two 8-bit latches or one 16-bit latch. Flow-through organization
of signal pins simplifies layout. All inputs are designed with hysteresis for
improved noise margin.
The inputs of FCT163373 can be driven from either 3.3V or 5V devices.
This feature allows the use of these transparent latches as translators in a
mixed 3.3V/5V supply system. With xLE inputs high, the FCT163373 can
be used as a buffer to connect 5V components to a 3.3V bus.
FUNCTIONAL BLOCK DIAGRAM
1
1
OE
48
1
LE
1
D
1
47
2
LE
2
OE
24
25
36
2
D
1
2
1
O
1
D
D
13
2
O
1
C
C
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2002 Integrated Device Technology, Inc.
MAY 2002
DSC-5416/2
IDT74FCT163373A/C
3.3V CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
1
LE
1
D
1
1
D
2
Description
Max
–0.5 to +4.6
–0.5 to 7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +60
Unit
V
V
V
°C
mA
V
TERM
(2)
Terminal Voltage with Respect to GND
1
OE
1
O
1
1
O
2
V
TERM
(3)
Terminal Voltage with Respect to GND
V
TERM
(4)
Terminal Voltage with Respect to GND
T
STG
I
OUT
Storage Temperature
DC Output Current
GND
1
O
3
1
O
4
GND
1
D
3
1
D
4
V
CC
1
O
5
1
O
6
V
CC
1
D
5
1
D
6
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Outputs and I/O terminals.
GND
1
O
7
1
O
8
2
O
1
2
O
2
GND
1
D
7
1
D
8
2
D
1
2
D
2
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max.
6
8
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
GND
2
O
3
2
O
4
GND
2
D
3
2
D
4
PIN DESCRIPTION
Pin Names
xDx
xLE
xOE
xOx
Description
Data Inputs
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-State Outputs
V
CC
2
O
5
2
O
6
V
CC
2
D
5
2
D
6
GND
2
O
7
2
O
8
2
OE
GND
2
D
7
2
D
8
2
LE
FUNCTION TABLE
(1)
xDx
H
L
X
X
Inputs
xLE
H
H
L
X
xOE
L
L
L
H
Outputs
xBx
H
L
O
(2)
Z
SSOP/ TSSOP
TOP VIEW
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2. Output level before the indicated steady-state input conditions were established.
2
IDT74FCT163373A/C
3.3V CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 2.7V to 3.6V
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
V
OH
Parameter
Input HIGH Level (Input pins)
Input HIGH Level (I/O pins)
Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Output HIGH Voltage
V
CC
= Min., I
IN
= –18mA
V
CC
= 3.3V, V
IN
= V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= 3.3V, V
IN
= V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 3V
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 3V
V
IN
= V
IH
or V
IL
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Short Circuit Current
(4)
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Max., V
O
= GND
(3)
—
–60
—
—
–135
150
0.1
–240
—
10
mA
mV
µA
I
OL
= 0.1mA
I
OL
= 16mA
I
OL
= 24mA
I
OL
= 24mA
—
—
—
—
—
0.2
0.3
0.3
0.2
0.4
0.55
0.5
V
I
OH
= –0.1mA
I
OH
= –3mA
I
OH
= –8mA
V
CC
= Max.
V
CC
= Max.
V
I
= 5.5V
V
I
= V
CC
V
I
= GND
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
(1)
Guaranteed Logic HIGH Level
Min.
2
2
–0.5
—
—
—
—
—
—
—
–36
50
V
CC
-0.2
2.4
2.4
(5)
Typ.
(2)
—
—
—
—
—
—
—
—
—
–0.7
–60
90
—
3
3
Max.
5.5
V
CC
+0.5
0.8
±1
±1
±1
±1
±1
±1
–1.2
–110
200
—
—
—
V
V
mA
mA
µA
µA
V
Unit
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH
= V
CC
–0.6V at rated current.
3
IDT74FCT163373A/C
3.3V CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= V
CC
–0.6V
(3)
V
CC
= Max.
Outputs Open
xOE = GND
One Input Toggling
50% Duty Cycle
V
CC
= Max., Outputs Open
f
i
= 10MHz
50% Duty Cycle
xOE = GND
xLE = V
CC
One Bit Toggling
V
CC
= Max., Outputs Open
f
i
= 2.5MHz
50% Duty Cycle
xOE = GND
xLE = V
CC
Sixteen Bits Toggling
V
IN
= V
CC
V
IN
= GND
Min.
—
—
Typ.
(2)
2
50
Max.
30
75
Unit
µA
µA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
–0.6V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
–0.6V
V
IN
= GND
—
0.5
0.8
mA
—
—
—
0.5
2
2
0.8
3
(5)
3.3
(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+ DI
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at fi
4
IDT74FCT163373A/C
3.3V CMOS 16-BIT TRANSPARENT LATCH
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1)
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
W
t
SK
(o)
Parameter
Propagation Delay
xDx to xOx
Propagation Delay
xLE to xOx
Output Enable Time
Output Disable Time
Set-up Time HIGH or LOW, xDx to xLE
Hold Time HIGH or LOW, xDx to xLE
xLE Pulse Width HIGH
Output Skew
(4)
Condition
(2)
C
L
= 50pF
R
L
= 500Ω
FCT163373A
Min.
(3)
Max.
1.5
5.2
2
1.5
1.5
2
1.5
5
—
8.5
6.5
5.5
—
—
—
0.5
FCT163373C
Min.
(3)
Max.
1.5
4.2
2
1.5
1.5
2
1.5
5
—
5.5
5.5
5
—
—
—
0.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Propagation Delays and Enable/Disable times are with V
CC
= 3.3V ±0.3V, Normal Range. For V
CC
= 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/Disable
times should be degraded by 20%.
2. See test circuit and waveforms.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5
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