M393B5270DH0-K00 datasheet, PDF

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M393B5270DH0-K00: DescriptionDDR DRAM Module, 512MX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240; Categorystorage storage; File Size2MB，55 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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M393B5270DH0-K00 Overview

DDR DRAM Module, 512MX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240

M393B5270DH0-K00 Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Parts packaging code	DIMM
package instruction	DIMM,
Contacts	240
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.225 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N240
length	133.35 mm
memory density	38654705664 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	240
word count	536870912 words
character code	512000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature
organize	512MX72
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	1.45 V
Minimum supply voltage (Vsup)	1.283 V
Nominal supply voltage (Vsup)	1.35 V
surface mount	NO
technology	CMOS
Temperature level	OTHER
Terminal form	NO LEAD
Terminal pitch	1 mm
Terminal location	DUAL

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Rev. 1.2, Aug. 2011

M393B5773DH0

M393B5273DH0

M393B5270DH0

M393B1K70DH0

M393B1K73DH0

M393B2K70DM0

240pin Registered DIMM

based on 2Gb D-die

1.35V

78FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed

herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung

Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property

right is granted by one party to the other party under this document, by implication, estoppel or other-

wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or

similar applications where product failure could result in loss of life or personal or physical harm, or any

military or defense application, or any governmental procurement to which special terms or provisions

may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

ⓒ

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Registered DIMM

datasheet

Rev. 1.2

DDR3L SDRAM

Table Of Contents

240pin Registered DIMM based on 2Gb D-die

1. DDR3L Registered DIMM Ordering Information ........................................................................................................... 5

2. Key Features................................................................................................................................................................. 5

3. Address Configuration .................................................................................................................................................. 5

4. Registered DIMM Pin Configurations (Front side/Back side)........................................................................................ 6

5. Pin Description ............................................................................................................................................................. 7

6. ON DIMM Thermal Sensor ........................................................................................................................................... 7

7. Input/Output Functional Description.............................................................................................................................. 8

8. Pinout Comparison Based On Module Type................................................................................................................. 9

9. Registering Clock Driver Specification .......................................................................................................................... 10

9.1 Timing & Capacitance values .................................................................................................................................. 10

9.2 Clock driver Characteristics ..................................................................................................................................... 10

10. Function Block Diagram: ............................................................................................................................................. 11

10.1 2GB, 256Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ................................................................... 11

10.2 4GB, 512Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ................................................................. 12

10.3 4GB, 512Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs) ................................................................... 13

10.4 8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs) ..................................................................... 14

10.5 8GB, 1Gx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs) .................................................................... 16

10.6 16GB, 2Gx72 Module (Populated as 4 ranks of x4 DDR3 SDRAMs) ................................................................... 17

11. Absolute Maximum Ratings ........................................................................................................................................ 22

11.1 Absolute Maximum DC Ratings............................................................................................................................. 22

11.2 DRAM Component Operating Temperature Range .............................................................................................. 22

12. AC & DC Operating Conditions................................................................................................................................... 22

12.1 Recommended DC Operating Conditions ............................................................................................................. 22

13. AC & DC Input Measurement Levels .......................................................................................................................... 23

13.1 AC & DC Logic Input Levels for Single-ended Signals .......................................................................................... 23

13.2 V

REF

Tolerances.................................................................................................................................................... 25

13.3 AC and DC Logic Input Levels for Differential Signals .......................................................................................... 26

13.3.1. Differential Signals Definition ......................................................................................................................... 26

13.3.2. Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................................. 26

13.3.3. Single-ended Requirements for Differential Signals ...................................................................................... 28

13.3.4. Differential Input Cross Point Voltage ............................................................................................................ 29

13.4 Slew Rate Definition for Single Ended Input Signals ............................................................................................. 30

13.5 Slew rate definition for Differential Input Signals ................................................................................................... 30

14. AC & DC Output Measurement Levels ....................................................................................................................... 30

14.1 Single Ended AC and DC Output Levels............................................................................................................... 30

14.2 Differential AC and DC Output Levels ................................................................................................................... 30

14.3 Single-ended Output Slew Rate ............................................................................................................................ 31

14.4 Differential Output Slew Rate ................................................................................................................................ 32

15. IDD specification definition.......................................................................................................................................... 33

16. IDD SPEC Table ......................................................................................................................................................... 35

17. Input/Output Capacitance ........................................................................................................................................... 38

18. Electrical Characteristics and AC timing ..................................................................................................................... 39

18.1 Refresh Parameters by Device Density................................................................................................................. 39

18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 39

18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 39

18.3.1. Speed Bin Table Notes .................................................................................................................................. 42

19. Timing Parameters by Speed Grade .......................................................................................................................... 43

19.1 Jitter Notes ............................................................................................................................................................ 46

19.2 Timing Parameter Notes........................................................................................................................................ 47

20. Physical Dimensions................................................................................................................................................... 48

20.1 256Mbx8 based 256Mx72 Module (1 Rank) - M393B5773DH0 ............................................................................ 48

20.1.1. x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs................................................................ 48

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M393B5270DH0-K00 Related Products

	M393B5270DH0-K00	M393B5270DH0-H90	M393B5773DH0-H90	M393B1K70DH0-K00	M393B2K70DM0-H90	M393B5273DH0-K00	M393B5773DH0-K00	M393B5273DH0-H90	M393B1K70DH0-H90	M393B1K73DH0-H90
Description	DDR DRAM Module, 512MX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 512MX72, 0.25ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 256KX72, 0.25ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 1GX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 2GX72, 0.25ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 512MX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 256KX72, 0.225ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 512MX72, 0.25ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 1GX72, 0.25ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240	DDR DRAM Module, 1GX72, 0.25ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
package instruction	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,	DIMM,
Contacts	240	240	240	240	240	240	240	240	240	240
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compli	compli
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	DUAL BANK PAGE BURST	FOUR BANK PAGE BURST	DUAL BANK PAGE BURST	SINGLE BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	0.225 ns	0.25 ns	0.25 ns	0.225 ns	0.25 ns	0.225 ns	0.225 ns	0.25 ns	0.25 ns	0.25 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240	R-XDMA-N240
length	133.35 mm	133.35 mm	133.35 mm	133.35 mm	133.35 mm	133.35 mm	133.35 mm	133.35 mm	133.35 mm	133.35 mm
memory density	38654705664 bit	38654705664 bit	18874368 bit	77309411328 bit	154618822656 bit	38654705664 bit	18874368 bit	38654705664 bit	77309411328 bi	77309411328 bi
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	72	72	72	72	72	72	72	72	72	72
Number of functions	1	1	1	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1	1	1	1
Number of terminals	240	240	240	240	240	240	240	240	240	240
word count	536870912 words	536870912 words	262144 words	1073741824 words	2147483648 words	536870912 words	262144 words	536870912 words	1073741824 words	1073741824 words
character code	512000000	512000000	256000	1000000000	2000000000	512000000	256000	512000000	1000000000	1000000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
organize	512MX72	512MX72	256KX72	1GX72	2GX72	512MX72	256KX72	512MX72	1GX72	1GX72
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
self refresh	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
Maximum supply voltage (Vsup)	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V	1.45 V
Minimum supply voltage (Vsup)	1.283 V	1.283 V	1.283 V	1.283 V	1.283 V	1.283 V	1.283 V	1.283 V	1.283 V	1.283 V
Nominal supply voltage (Vsup)	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V	1.35 V
surface mount	NO	NO	NO	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL

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