PL123-09OCA datasheet, PDF - EEWORLD Datasheet

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PL123-09OCA: DescriptionIC,CLOCK DRIVER,1:8 OUTPUT,TSSOP,16PIN,PLASTIC; Categorylogic logic; File Size327KB，10 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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PL123-09OCA Overview

IC,CLOCK DRIVER,1:8 OUTPUT,TSSOP,16PIN,PLASTIC

PL123-09OCA Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microchip
package instruction	TSSOP, TSSOP16,.25
Reach Compliance Code	compliant
Input adjustment	STANDARD
JESD-30 code	R-PDSO-G16
length	5 mm
Load capacitance (CL)	30 pF
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
MaximumI(ol)	0.012 A
Number of functions	1
Number of inverted outputs
Number of terminals	16
Actual output times	9
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP16,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TUBE
power supply	3.3 V
Maximum supply current (ICC)	32 mA
Prop。Delay @ Nom-Sup	0.35 ns
propagation delay (tpd)	0.35 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.25 ns
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	4.4 mm
minfmax	10 MHz

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(Preliminary)

Low Skew Zero Delay Buffer

FEATURES



Frequency Range 10MHz to 134 MHz

Output Options:

5 outputs

PL123-05

9 outputs

PL123-09

Zero input - output delay

Optional Drive Strength:

Standard (8mA)

PL123-05/-09

High (12mA)

PL123-05H/-09H

3.3V, ±10% operation

Available in Commercial and Industrial temperature

ranges

Available in 16-Pin SOP or TSSOP (PL123-09),

and 8-Pin SOP (PL123-05) packages

DESCRIPTION

The PL123-05/-09 (-05H/-09H for High Drive) are high

performance, low skew, low jitter zero delay buffers

designed to distribute high speed clocks. They have

one (PL123-05) or two (PL123-09) low-skew output

banks, of 4 outputs each, that are synchronized with

the input. The PL123-09 allows control of the banks of

outputs by using the S1 and S2 inputs as shown in the

Selector Definition table on page 2.

The synchronization is established via CLKOUT feed

back to the input of the PLL. Since the skew between

the input and output is less than

100ps,

the device

acts as a zero delay buffer. The input output propaga-

tion delay can be advanced or delayed by adjusting the

load on the CLKOUT pin.

These parts are not intended for 5V input-tolerant ap-

plications.

BLOCK DIAGRAM

REF

PLL

Mux

CLKOUT

CLKA1

CLKA2

CLKA3

REF

CLKA2

CLKA1

GND

CLKOUT

CLKA4

VDD

CLKA3

REF

CLKA4

CLKB1

CLKA1

CLKA2

VDD

GND

CLKB1

CLKB3

CLKB4

CLKB2

CLKOUT

CLKA4

CLKA3

VDD

GND

CLKB4

CLKB3

Selector

Inputs

(PL123-09 Only)

CLKB2

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com

Rev 4/9/08 Page 1

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