EEWORLDEEWORLDEEWORLD

Part Number

Search

0603CG101K0B200

Description
CAPACITOR, CERAMIC, MULTILAYER, 100V, C0G, 0.0001uF, SURFACE MOUNT, 0603, CHIP, ROHS COMPLIANT
CategoryPassive components    capacitor   
File Size390KB,17 Pages
ManufacturerYAGEO
Websitehttp://www.yageo.com/
Environmental Compliance  
Download Datasheet Parametric View All

0603CG101K0B200 Overview

CAPACITOR, CERAMIC, MULTILAYER, 100V, C0G, 0.0001uF, SURFACE MOUNT, 0603, CHIP, ROHS COMPLIANT

0603CG101K0B200 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerYAGEO
package instruction, 0603
Reach Compliance Codeunknown
ECCN codeEAR99
capacitance0.0001 µF
Capacitor typeCERAMIC CAPACITOR
dielectric materialsCERAMIC
JESD-609 codee3
Manufacturer's serial numberNPO
Installation featuresSURFACE MOUNT
multi-layerYes
negative tolerance10%
Number of terminals2
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Package shapeRECTANGULAR PACKAGE
method of packingTR, PAPER, 7 INCH
positive tolerance10%
Rated (DC) voltage (URdc)100 V
size code0603
surface mountYES
Temperature characteristic codeC0G
Temperature Coefficient-/+30ppm/Cel ppm/°C
Terminal surfaceTin (Sn)
Terminal shapeWRAPAROUND
w
DATA SHEET
SURFACE-MOUNT CERAMIC
MULTILAYER CAPACITORS
Mid-voltage: NP0/X7R
(Pb Free & RoHS compliant)
100 V TO 500 V
10 pF to 470 nF
Product specification – Sep 08, 2005 V. 0
DC servo motor driver is still very good
...
led2015 Motor Drive Control(Motor Control)
The 4.3-inch screen is finally done
After a Spring Festival preparation, and buying a few other people's boards for reference, I finally lit up the 4.3-inch screen. The control part of this board is the STM32 chip, and then the dedicate...
fsyicheng FPGA/CPLD
Please tell me about MDD/PDD
Experts, I am not very clear about MS's MDD/PDD. Since it is a layered driver, are there any interface definitions for the MDD layer and the interface definitions for the PDD layer? Where are those in...
游客 Embedded System
Kernel compilation VGA configuration
After I compiled the HPS kernel, I found that VGA display was available before, but now it doesn't work. I guessed that the VGA module might not be configured, but I didn't find any configuration abou...
的神等等 FPGA/CPLD
Simple circuit analysis
What is VREF in this formula? This is a voltage regulator output chip, and that potentiometer is a digitalpotentiometer....
sxp雨落 Analog electronics
Which dsp development board is the best
A newbie wants to learn DSP by himself but doesn't know how to learn it. He wants to buy a development board or solder the development board by himself in a minimum system, find a book, and find a mas...
傻傻的熊猫 DSP and ARM Processors

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1353  1686  1538  555  2078  28  34  31  12  42 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号