BtT9170
Intelligent T1 Controller
Product Description
The BtT9170 Intelligent T1 Controller is a microprocessor (MPU) controlled
device which implements a T1 interface between the multiplexed digital DS1 sig-
nal and the PCM highway of digital voice and data system equipment. The
BtT9170 handles both D4 (SF) and D5 (ESF) standards with Facility Data Link
(FDL) used in T1, ISDN primary-rate, and digital carrier systems.
Designers are provided a cost-effective solution for T1/ISDN primary-rate
interface that integrates complex functions to minimize system development time,
component count, board space, and cost. Combining dedicated control pins with
MPU-addressable registers, maximum functional control is achieved with mini-
mal MPU intervention. The BtT9170 provides direct control over the Bt8069-
series line interface unit (LIU).
Use of a memory-mapped microprocessor bus interface minimizes the host
MPU real-time requirement. Direct MPU access to T1 control and monitor func-
tions in the BtT9170 register map allows software access without complicated
serial message protocols.
Distinguishing Features
•
•
Intelligent Single-Device DS1 T-Carrier
Transceiver (1.544 MHz)
Compatible with ANSI Standard
T1.403 Covering Facility Data Link
Operations:
– Priority Codeword Handling
– Near-End and Far-End Perfor-
mance Monitoring
– Extracted Link Data Handling
Signalling Register Bank
Independent Transmit and Receive
Per-Channel Conditioning
– Automatic Conditioning of Receive
Trunk and Signalling During CGA
– Unconditional Replacement of
Transmit or Receive Trunk and Sig-
nalling
Dedicated per-channel control register
for each time slot
80x88-Compatible Parallel Micropro-
cessor Bus Interface
– 8-Bit Address/Data Bus for Access-
ing Control and Status Information
Separate Serial Interfaces for DS1
Transmit & Receive Data
Microprocessor-Accessible Registers
– 16 Control and Monitor
– 14 Facility Data Link
– 24 Per-Channel Control
– 12 Received Signalling
User-Maskable Interrupt Request
Generated on Specified Alarm and
Error Conditions
Independent Transmit and Receive
Functions, Each With a Separate
Timebase
Off-line Framer Flywheel Timebase
Option
Implements T1 Formats With and
Without Signalling
– ESF: 24 Frames/Multiframe
– SF: 12 Frames/Multiframe
– N: 4 Frames/Multiframe
- continued
•
•
•
BtT9170 Functional System Interface
TX
Bt8069
Series
Line
Interface
Unit (LIU)
2 RX
Control
5 Status
2
2
BtT9170
Intelligent
T1
Controller
FDLC RX
FDLC TX
Facility
Data
Link
Control
•
•
•
80X88
Micro-
Processor
Bus
ADDRESS/DATA BUS
CONTROL BUS
T1 RSER
T1 TSER
T1
Data Bit
Stream
Processor
& System
•
•
•
•
Brooktree
®
Brooktree Corporation • 9868 Scranton Road • San Diego, CA 92121-3707 • 619-452-7580
1-800-2-BT-APPS • FAX: 619-452-1249 • Internet: apps@brooktree.com • LT917001 Rev. B
Distinguishing Features
(continued)
• Zero-Suppression Modes
– Bit-7 Stuffing
– B8ZS Line Coding
– Transparent
Meets CCITT G.733 (1.544 MHz) and Applicable
Sections of G.703
Compatible with AT&T Technical Advisories on ESF
and Clear-Channel Operation With B8ZS
Alarm Generation and Detection
Remote and Locally Controlled Payload Loopback
Pin-For-Pin Compatible with BtP9170, Intelligent El
Framer
Direct Interface and Control of the Bt8069-series Line
Interface Unit (LIU)
Direct Interface to the Bt8071A 32-Channel HDLC
Controller
Packages:
– 40-pin Plastic (DIP)
– 44-pin Plastic (PLCC) Package
Operates From a Single +5 Vdc
±
5% Power Supply
CMOS/TTL-Compatible Inputs and Outputs
Low-Power CMOS Technology
•
•
•
•
•
•
•
•
•
•
•
Ordering Information
Model Number
BtT9170KP
BtT9170KPJ
Package
40-pin Plastic DIP
44-pin Plastic Leaded Chip Carrier (PLCC)
Ambient Temperature
0
°
C to 70
°
C (Commercial)
0
°
C to 70
°
C (Commercial)
Consult factory about extended temperature availability.
Copyright
©
1993 Brooktree Corporation. All rights reserved.
Print date: January, 1997
Brooktree reserves the right to make changes to its products or specifications to improve performance, reliability, or
manufacturability. Information furnished by Brooktree Corporation is believed to be accurate and reliable. However, no
responsibility is assumed by Brooktree Corporation for its use; nor for any infringement of patents or other rights of third parties
which may result from its use. No license is granted by its implication or otherwise under any patent or patent rights of Brooktree
Corporation.
Brooktree products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a
Brooktree product can reasonably be expected to result in personal injury or death. Brooktree customers using or selling Brooktree
products for use in such applications do so at their own risk and agree to fully indemnify Brooktree for any damages resulting from
such improper use or sale.
Brooktree is a registered trademark of Brooktree Corporation. Product names or services listed in this publication are for
identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks
mentioned herein are the property of their respective holders.
Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
Table of Contents
List of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
Product Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Facility Data Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Per-Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transceiver and Off-line Framer (Flywheel Timebase) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Interface Unit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Framing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Line Codes/Zero Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
2
2
2
2
2
Pin Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Introduction
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Transmit Section
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Transmit Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Frame/Multiframe Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Input Register/B8ZS Decoder and Bipolar Violation Detector . . . . . . . . . . . . . .
Receive Extractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Off-line Framer/RSYNC Multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
14
14
16
17
18
22
23
Receive Section
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Facility Data Link Section
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Transmit FDL Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
Receive FDL Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
Line Interface Unit (LIU) Control Section
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Peripheral I/O Section
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Brooktree
®
iii
Table of Contents
BtT9170
Microprocessor Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Asynchronous MPU Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Monitor Register Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Per-Channel Control Register Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Received Signalling Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
31
32
32
32
Internal Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Monitor Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Monitor Register 0 (MR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
Monitor Register 1 (MR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
Monitor Register 2 (MR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
Priority Codeword Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Receive Priority Codeword Register (RPCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
Transmit Priority Codeword Register (TPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
Control Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Control Register 0 (CR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register 1 (CR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register 2 (CR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register 3 (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register 4 (CR4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Register 5 (CR5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Idle Register (IR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Signalling Register (DSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
42
43
44
45
46
48
49
Interrupt Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Alarm Enable Register (AER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
Interrupt Enable Register (IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
Interrupt Cause Register (ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
Per-Channel Control Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Architecture Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Default Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Data Flow Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Data Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signalling Conditioning or Force . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Force. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Signalling Array Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Signalling Array A (RSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Signalling Array B (RSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Signalling Array C (RSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Signalling Array D (RSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
51
51
51
52
52
52
52
52
53
53
53
53
Received Signalling Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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BtT9170
Table of Contents
Near-End Monitor Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Near-End Monitor Registers 1 and 2 (NEMR1 and NEMR2) . . . . . . . . . . . . . . . . . . . . . .
54
Near-End Monitor Registers 3 and 4 (NEMR3 and NEMR4) . . . . . . . . . . . . . . . . . . . . . .
54
Near-End Monitor Registers 5 and 6 (NEMR5 and NEMR6) . . . . . . . . . . . . . . . . . . . . . .
55
Far-End Performance Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Far-End Performance Registers 1 and 2 (FEPR1 and FEPR2) . . . . . . . . . . . . . . . . . . . . .
Far-End Performance Registers 3 and 4 (FEPR3 and FEPR4) . . . . . . . . . . . . . . . . . . . . .
Far-End Performance Registers 5 and 6 (FEPR5 and FEPR6) . . . . . . . . . . . . . . . . . . . . .
Far-End Performance Registers 7 and 8 (FEPR7 and FEPR8) . . . . . . . . . . . . . . . . . . . . .
55
56
56
56
Switching Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Microprocessor Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Transmit Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Receiver Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Clock and Data Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Reset Timing
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Reframe Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extracted Link DataTiming–ESF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Link Data Timing–ESF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alarm-to-Interrupt Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RRED Interrupt—MPU Read and Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Priority Codeword Response Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
68
68
69
69
70
Absolute Maximum Ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Electrical Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Package Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Mechanical Drawings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Revision History
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Appendix A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
TI Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signalling Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alarms and Error Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
75
76
76
Superframe Format (SF)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Extended Superframe Format (ESF)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Nonsignalling Format (N)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Appendix B
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Facility Data Link (FDL)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Bit-Oriented Data (Priority Codeword) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
Message-Oriented Data (Performance Reports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
Brooktree
®
v
Embedded System
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