MT9079APR1 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Wireless rf/communication> Telecom circuit> MT9079APR1

MT9079APR1: DescriptionFramer, CMOS, PQCC44,; CategoryWireless rf/communication Telecom circuit; File Size980KB，75 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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MT9079APR1 Overview

Framer, CMOS, PQCC44,

MT9079APR1 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microsemi
Parts packaging code	LPCC
package instruction	QCCJ, LDCC44,.7SQ
Contacts	44
Reach Compliance Code	compliant
JESD-30 code	S-PQCC-J44
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	5 V
Certification status	Not Qualified
Maximum slew rate	0.011 mA
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	FRAMER
Temperature level	INDUSTRIAL
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD

MT9079APR1 Preview

CMOS ST-BUS

Family

MT9079

Advanced Controller for E1

Data Sheet

Features

•

Meets applicable requirements of CCITT

G.704, G.706, G.732, G.775, G.796, I.431 and

ETSI ETS 300 011

HDB3, RZ, NRZ (fibre interface) and bipolar

NRZ line codes

Data link access and national bit buffers (five

bytes each)

Enhanced alarms, performance monitoring and

error insertion

Maskable interrupts for alarms, receive CAS bit

changes, exception conditions and counter

overflows

Automatic interworking between CRC-4 and

non-CRC-4 multiframing

Dual transmit and receive 16 byte circular

channel buffers

Two frame receive elastic buffer with controlled

slip direction indication and 26 channel

hysteresis (208 UI wander tolerance)

CRC-4 updating algorithm for intermediate path

points of a message-based data link application

Ordering Information

MT9079AE

40 Pin PDIP

MT9079AL

44 Pin QFP

MT9079AP

44 Pin PLCC

MT9079APR

44 Pin PLCC

MT9079AP1

44 Pin PLCC*

MT9079APR1 44 Pin PLCC*

*Pb Free Matte Tin

-40°C to +85°C

July 2005

•

Tubes

Trays

Tubes

Tape & Reel

Tubes

Tape & Reel

•

CO and PABX switching equipment interfaces

E1 add/drop multiplexers and channel banks

Test equipment and satellite interfaces

•

Description

The MT9079 is a feature rich E1 (PCM 30, 2.048

Mbps) link framer and controller that meets the latest

CCITT and ETSI requirements.

The MT9079 will interface to a 2.048 Mbps backplane

and can be controlled directly by a parallel processor,

serial controller or through the ST-BUS.

Extensive alarm transmission and reporting, as well as

exhaustive performance monitoring and error

diagnostic features make this device ideal for a wide

variety of applications.

•

Applications

•

Primary rate ISDN network nodes

Digital Access Cross-connect (DACs)

TxMF

RxMF

DSTi

DSTo

Transmit & Receive

Data

Interface

Frame MUX/DEMUX

2 Frame Rx

Elastic

Buffer With

Slip Control

PCM 30

(E1)

Link

Interface

TAIS

TxA

TxB

RxA

RxB

TxDL

RxDL

DLCLK

Data

Link

Buffer

National

Bit

Buffer

Dual 16

Byte Rx

Buffer

Dual 16

Byte Tx

Buffer

Control

Port

Interface

(fig. 3)

Control

Interface

ABCD

Signal

Buffer

Test

Code

Gen.

Performance

Monitoring &

Alarm

Control

Phase

Detector

256

Circuit

Timing

E2i

E8Ko

C4i/C2i

F0i

ST-BUS Timing

Circuit

Timing

to all registers

and counters

RESET

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

MT9079

DLCLK

TxDL

RxDL

DSTo

RESET

TxA

TxB

TAIS

CSTo1

IRQ

D0\SIO\CSTo0

VDD

Data Sheet

40 PIN PLASTIC DIP

DLCLK

TxDL

RxDL

DSTo

RESET

TxA

TxB

TAIS

CSTo1

IRQ

D0\SIO\CSTo0

VDD

CSTi2

VSS

S/P

TxMF

RxMF

DSTi

E8Ko

F0i

RxA

RxB

A4\ST/SC

AC3

AC2

AC1

AC0

R/W\RxD\CSTi0

DS\SCLK\CSTi1

C4i/C2i

E2i

44 PIN PLCC

Figure 2 - Pin Connection

Zarlink Semiconductor Inc.

A4\ST/SC

AC3

AC2

AC1

AC0

R/W\RxD\CSTi0

DS\SCLK\CSTi1

C4i/C2i

E2i

44 PIN QFP

RESET

DSTo

RxDL

TxDL

DLCLK

IRQ

D0\SIO\CSTo0

VDD

AC4\ST/SC

AC3

AC2

AC1

AC0

TxA

TxB

TAIS

CSTo1

CSTi2

VSS

S/P

TxMF

RxMF

DSTi

E8Ko

F0i

RxA

RxB

E2i

C4i/C2i

DS\SCLK\CSTi1

R/W\RxD\CSTi0

CSTi2

VSS

S/P

TxMF

RxMF

DSTi

E8Ko

F0i

RxA

RxB

MT9079

Pin Description

Pin #

DIP

PLCC

QFP

Data Sheet

Name

Description (see notes 1, 2 and 3)

RESET

RESET (Input):

Low - maintains the device in a reset condition. High - normal operation. The

MT9079 should be reset after power-up. The time constant for a power-up reset circuit (see

Figure 11) must be a minimum of five times the rise time of the power supply. In normal

operation, the RESET pin must be held low for a minimum of 100 nsec. to reset the device.

DSTo

RxDL

Data ST-BUS (Output):

A 2.048 Mbit/s serial output stream which contains the 30 PCM or

data channels received from the PCM 30 line. See Figure 4b.

Receive Data Link (Output):

A 4 kbit/s serial stream which is demultiplexed from a selected

national bit (non-frame alignment signal) of the PCM 30 receive signal. Received DL data is

clocked out on the rising edge of DLCLK, see Figure 20.

Transmit Data Link (Input):

A 4 kbit/s serial stream which is multiplexed into a selected

national bit (non-frame alignment signal) of the PCM 30 transmit signal. Transmit DL data is

clocked in on the rising edge of internal clock IDCLK, see Figure 21.

TxDL

DLCLK

Data Link Clock (Output):

A 4 kHz clock signal used to clock out DL data (RxDL) on its

rising edge. It can also be used to clock DL data in and out of external serial controllers (i.e.,

MT8952). See TxDL and RxDL pin descriptions.

IRQ

No Connection.

Interrupt Request (Output):

Low - interrupt request. High - no interrupt request.

IRQ is an open drain output that should be connected to V

through a pull-up resistor. An

active CS signal is not required for this pin to function. This pin should be left open when the

ST-BUS control port is selected.

Data 0 (Three-state I/O):

The least significant bit of the bidirectional data bus of the parallel

processor interface.

Serial Input/Output (Three state I/O):

This pin function is used in serial controller mode and

can be configured as control data input/output for Intel operation (connect to controller pin

RxD). Input data is sampled LSB first on the rising edge of SCLK; data is output LSB first on

the falling edge of SCLK. It can also be configured as the control data output for Motorola and

National Microwire operation (data output MSB first on the falling edge of SCLK). See CS pin

description.

[P]

SIO

[S]

CSTo0

Control ST-BUS Zero (Output):

A 2.048 Mbit/s serial status stream which provides device

[ST] status, performance monitoring, alarm status and phase status data.

8-14 9-15 3-9

D1-D7

Data 1 to Data 7 (Three-state I/O):

These signals, combined with D0, form the bidirectional

[P]

data bus of the parallel processor interface (D7 is the most significant bit).

AC4

[P]

ST/SC

[ST S]

Positive Power Supply (Input):

+5V

10%.

No Connection.

Address/Control 4 (Input):

The most significant address and control input for the non-

multiplexed parallel processor interface.

ST-BUS/Serial Controller (Input):

High - selects ST-BUS mode of operation.

Low - selects serial controller mode of operation.

Zarlink Semiconductor Inc.

MT9079

Pin Description (continued)

Pin #

DIP

PLCC

QFP

Data Sheet

Name

13-

AC3-

AC0

[P]

R/W

[P]

RxD

[S]

Description (see notes 1, 2 and 3)

Address/Control 3 to 0 (Inputs):

Address and control inputs for the non-multiplexed

parallel processor interface. AC0 is the least significant input.

Read/Write (Input):

High - the parallel processor is reading data from the MT9079.

Low - the parallel processor is writing data to the MT9079.

Receive Data (Input):

This pin function is used in Motorola and National Microwire serial

controller mode. Data is sampled on the rising edge of SCLK, MSB first. See CS pin

description.

Control ST-BUS Zero (Input):

A 2.048 Mbit/s serial control stream which contains the

device control, mode selection, and performance monitoring control.

Chip Select (Input):

Low - selects the MT9079 parallel processor or serial controller

interface. High - the parallel processor or serial controller interface is idle and all bus I/O

pins will be in a high impedance state. When controller mode is selected, the SCLK input is

sampled when CS is brought low. If SCLK is high the device in is Intel mode; if SCLK is

low it will be in Motorola/National Microwire mode. This pin has no function (NC) in ST-

BUS mode.

Data Strobe (Input):

This input is the active low data strobe of the parallel processor

interface.

Serial Clock (Input):

This is used in serial controller mode to clock serial data in and out

of the MT9079 on RxD and SIO. If SCLK is high when CS goes low, the device will be in

Intel mode; if SCLK is low when CS goes low, it will be in Motorola/National Microwire

mode.

Control ST-BUS One (Input):

A 2.048 Mbit/s serial control stream which contains the per

timeslot control programming.

17-

19-

CSTi0

[ST]

[SP]

[P]

SCLK

[S]

CSTi1

[ST]

C4i/C2i

4.096 MHz and 2.048 MHz System Clock (Input):

This is master clock for the serial PCM

data and ST-BUS sections of the MT9079. The MT9079 automatically detects whether a 4.096

or 2.048 MHz clock is being used. See Figure 22 for timing information.

E2i

RxB

RxA

F0i

E8Ko

2.048 MHz Extracted Clock (Input):

This clock is extracted from the received signal. Its

rising edge is used internally to clock in data received on RxA and RxB. See Figure 29.

No Connection.

Receive B (Input):

Received split phase unipolar signal decoded from a bipolar line

receiver. Receives RZ and NRZ bipolar signals. See Figures 29 and 31.

Receive A (Input):

Received split phase unipolar signal decoded from a bipolar line

receiver. Receives RZ and NRZ bipolar signals. See Figurs 29 and 31.

Frame Pulse (Input):

This is the ST-BUS frame synchronization signal which delimits the

32 channel frame of all ST-BUS streams, as well as DSTi and DSTo in all modes.

Extracted 8 kHz Clock (Output):

An 8 kHz signal generated by dividing the extracted

2.048 MHz clock (E2i) by 256 and aligning it with the received PCM 30 frame. The 8 kHz

signal can be used to synchronize the system clock with the extracted 2.048 MHz clock.

E8Ko is high when 8KSEL=0. See Figure 27.

Zarlink Semiconductor Inc.

MT9079

Pin Description (continued)

Pin #

DIP

PLCC

QFP

Data Sheet

Name

DSTi

RxMF

Description (see notes 1, 2 and 3)

Data ST-BUS (Input).

A 2.048 Mbit/s serial stream which contains the 30 PCM or data

channels to be transmitted on the PCM 30 line. See Figure 4a.

Receive Multiframe Boundary (Output):

An output pulse delimiting the received multiframe

boundary. The next frame output on the data stream (DSTo) is basic frame zero on the PCM 30

link. This receive multiframe signal can be related to either the receive CRC multiframe

(MFSEL=1) or the receive signalling multiframe (MFSEL=0).

See Figures 25 and 26.

Transmit Multiframe Boundary (Input):

This input is used to set the channel associated and

CRC transmit multiframe boundary. The device will generate its own multiframe if this pin is

held high. This input is pulled high in most applications. See Figures 24 to 26.

Serial/Parallel (Input):

High - serial controller port or ST-BUS operation.

Low - parallel processor port operation.

Negative Power Supply (Input):

Ground.

Control ST-BUS Input Two (Input):

A 2.048 Mbit/s ST-BUS control stream which contains

the 30 (ABCDXXXX) transmit signalling nibbles when RPSIG=0. When RPSIG=1 this pin

has no function. Only the most significant nibbles of each ST-BUS timeslot are valid. See

Figure 4c.

No Connection.

TxMF

S/P

CSTi2

CSTo1

Control ST-BUS Output One (Output):

A 2.048 Mbit/s serial status stream which provides

the 30 (ABCDABCD) receive signalling nibbles. See Tables 15 - 17.

TAIS

TxB

Transmit Alarm Indication Signal (Input):

High - TxA and TxB will transmit data normally.

Low - TxA and TxB transmits an AIS (all ones signal).

Transmit B (Output):

A split phase unipolar signal suitable for use with TxA, an external line

driver and a transformer to construct a bipolar PCM 30 line signal. This output can also

transmit RZ and NRZ bipolar signals. See Figures 28 and 30.

Transmit A (Output):A

split phase unipolar signal suitable for use with TxB, an external line

driver and a transformer to construct a bipolar PCM 30 line signal. This output can also

transmit RZ and NRZ bipolar signals. See Figures 28 and 30.

Internal Connection (Input):

Connect to ground for normal operation.

TxA

Note: 1.All inputs are CMOS with TTL compatible logic levels.

Note: 2.All outputs are CMOS and are compatible with both TTL and CMOS logic levels.

Note: 3.See AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels for input and output voltage thresholds.

Zarlink Semiconductor Inc.

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MT9079APR1 Related Products

	MT9079APR1	MT9079AP1	MT9079APR
Description	Framer, CMOS, PQCC44,	Framer	Framer
Maker	Microsemi	Microsemi	Microsemi
Parts packaging code	LPCC	LPCC	LPCC
Contacts	44	44	44
Reach Compliance Code	compliant	compliant	compliant
Telecom integrated circuit types	FRAMER	FRAMER	FRAMER

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