35(/,0,1$5< 7(&+1,&$/ '$7$
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Preliminary Technical Data
ADSP-219x DSP CORE FEATURES
6.25 ns Instruction Cycle Time (Internal), for up to
160 MIPS Sustained Performance
ADSP-218x Family Code Compatible with the Same
Easy -to-Use Algebraic Syntax
Single-Cycle Instruction Execution
Up to 16M words of Addressable Memory Space with
24 Bits of Addressing Width
Dual Purpose Program Memory for Both Instruction and
Data Storage
Fully Transparent Instruction Cache Allows Dual
Operand Fetches in Every Instruction Cycle
Unified Memory Space Permits Flexible Address
Generation, Using Two Independent DAG Units
DSP Microcomputer
ADSP-2195
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units with Dual 40-bit
Accumulators
Single-Cycle Context Switch between Two Sets of
Computational and DAG Registers
Parallel Execution of Computation and Memory
Instructions
Pipelined Architecture Supports Efficient Code
Execution at Speeds up to 160 MIPS
Register File Computations with All Nonconditional,
Nonparallel Computational Instructions
Powerful Program Sequencer Provides Zero-Overhead
Looping and Conditional Instruction Execution
Architectural Enhancements for Compiled C
Code Efficiency
FUNCTIONAL BLOCK DIAGRAM
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REV. PrA
This information applies to a product under development. Its characteristics
and specifications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise
agreed to in writing.
One Technology Way, P
.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
World Wide Web Site: http://www.analog.com
Fax:781/326-8703
©Analog Devices,Inc., 2001
35(/,0,1$5< 7(&+1,&$/ '$7$
ADSP-2195
For current information contact Analog Devices at 800/262-5643
September 2001
ADSP-2195 DSP FEATURES
32K Words of On-Chip RAM, Configured as 16K Words
On-Chip 24-bit RAM and 16K Words On-Chip
16-bit RAM
16K Words of On-Chip 24-bit ROM
Architecture Enhancements beyond ADSP-218x Family
are Supported with Instruction Set Extensions for
Added Registers, Ports, and Peripherals
Flexible Power Management with Selectable
Power-Down and Idle Modes
Programmable PLL Supports 1 to 32 Frequency
Multiplication, Enabling Full-Speed Operation from
Low-Speed Input Clocks
2.5 V Internal Operation Supports 3.3 V Compliant I/O
Three Full-Duplex Multichannel Serial Ports, Each
Supporting H.100 Standard with A-Law and -Law
Companding in Hardware
Two SPI-Compatible Ports with DMA Capability
One UART Port with DMA Capability
16 General-Purpose I/O Pins (Eight Dedicated/Eight
Programmable from the External Memory Interface)
with Integrated Interrupt Support
Three Programmable 32-Bit Interval Timers with
Pulsewidth Counter, PWM Generation, and Externally
Clocked Timer Capabilities
Up to 11 DMA Channels can be Active at any Given Time
Host Port With DMA Capability for Efficient, Glueless Host
Interface (16-Bit Transfers)
External Memory Interface Features Include:
Direct Access from the DSP to External Memory for
Data and Instructions.
Support for DMA Block Transfers to/from
External Memory.
Separate Peripheral Memory Space with Parallel
Support for 224K External 16-Bit Registers.
Four General-Purpose Memory Select Signals that
Provide Access to Separate Banks of External
Memory. Bank Boundaries and Size Are User-
Programmable.
Programmable Waitstate Logic with ACK Signal and
Separate Read and Write Wait Counts. Wait Mode
Completion Supports All Combinations of ACK
and/or Wait Count.
I/O Clock Rate Can Be Set to the Peripheral Clock Rate
Divided by 1, 2, 4, 16, or 32 to Allow Interface to Slow
Memory Devices.
Address Translation and Data Word Packing is Provided
to Support an 8- or 16-Bit External Data Bus.
Programmable Read and Write Strobe Polarity.
Separate Configuration Registers for the Four
General-Purpose, Peripheral, and Boot
Memory Spaces.
Bus Request and Grant Signals Support the Use of the
External Bus by an External Device.
Boot Methods Include Booting Through External Memory
Interface, SPI Ports, UART Port, or Host Interface
IEEE JTAG Standard 1149.1 Test Access Port Supports
On-Chip Emulation and System Debugging
144-Lead LQFP Package (20 20 1.4 mm) and 144-Lead
Mini-BGA Package (10 10 1.25 mm)
2
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
REV. PrA
35(/,0,1$5< 7(&+1,&$/ '$7$
September 2001
For current information contact Analog Devices at 800/262-5643
ADSP-2195
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TABLE OF CONTENTS
ADSP-219x dSP Core Features . . . . . . . . . . . . . . . . . 1
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . 2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . 4
DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . . 5
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 6
Internal (On-Chip) Memory . . . . . . . . . . . . . . . . 6
Internal On-Chip ROM . . . . . . . . . . . . . . . . . . . . 6
On-Chip Memory Security . . . . . . . . . . . . . . . . . 7
External (Off-Chip) Memory . . . . . . . . . . . . . . . . 8
External Memory Space . . . . . . . . . . . . . . . . . . . . 8
I/O Memory Space . . . . . . . . . . . . . . . . . . . . . . . 8
Boot Memory Space . . . . . . . . . . . . . . . . . . . . . . 8
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Host Port Acknowledge (HACK) Modes . . . . . . 10
Host Port Chip Selects . . . . . . . . . . . . . . . . . . . 11
DSP Serial Ports (SPORTs) . . . . . . . . . . . . . . . . . . . 11
Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . 11
UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Programmable Flag (PFx) Pins . . . . . . . . . . . . . . . . . 12
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . 13
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-down Core Mode . . . . . . . . . . . . . . . . . . 13
Power-Down Core/Peripherals Mode . . . . . . . . . 13
Power-Down All Mode . . . . . . . . . . . . . . . . . . . 13
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . . 16
Instruction Set Description . . . . . . . . . . . . . . . . . . . . 16
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . 16
Designing an Emulator-Compatible DSP Board
(Target) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Target Board Header . . . . . . . . . . . . . . . . . . . . . 17
JTAG Emulator Pod Connector . . . . . . . . . . . . 18
Design-for-Emulation Circuit Information . . . . . 18
Additional Information . . . . . . . . . . . . . . . . . . . . . . . 18
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Recommended Operating Conditions . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . .
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . .
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . .
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . .
Clock In and Clock Out Cycle Timing . . . . . . .
Programmable Flags Cycle Timing . . . . . . . . . .
Timer PWM_OUT Cycle Timing . . . . . . . . . . .
External Port Write Cycle Timing . . . . . . . . . . .
External Port Read Cycle Timing . . . . . . . . . . .
External Port Bus Request and Grant Cycle
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Host Port ALE Mode Write Cycle Timing . . . .
Host Port ACC Mode Write Cycle Timing . . . .
Host Port ALE Mode Read Cycle Timing . . . . .
Host Port ACC Mode Read Cycle Timing . . . .
Serial Port (SPORT) Clocks and Data Timing .
Serial Port (SPORT) Frame Synch Timing . . . .
Serial Peripheral Interface (SPI) Port—Master
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface (SPI) Port—Slave
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Universal Asynchronous Receiver-Transmitter
(UART) Port—Receive and Transmit
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG Test And Emulation Port Timing . . . . . .
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . .
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Disable Time . . . . . . . . . . . . . . . . . . . .
Output Enable Time . . . . . . . . . . . . . . . . . . . . .
Example System Hold Time Calculation . . . . . .
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . .
Environmental Conditions . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics . . . . . . . . . . . . . . . . . .
ADSP-2195 144-Lead LQFP Pinout . . . . . . . . . . . .
ADSP-2195 144-Lead Mini-BGA Pinout . . . . . . . .
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
3
35(/,0,1$5< 7(&+1,&$/ '$7$
ADSP-2195
For current information contact Analog Devices at 800/262-5643
September 2001
General Note
This data sheet provides preliminary information for the
ADSP-2195 Digital Signal Processor.
GENERAL DESCRIPTION
• Receive or transmit data over two SPI ports
• Access external memory through the external memory
interface
• Decrement the timers
DSP Core Architecture
The ADSP-2195 instruction set provides flexible data
moves and multifunction (one or two data moves with a
computation) instructions. Every single-word instruction
can be executed in a single processor cycle. The ADSP-2195
assembly language uses an algebraic syntax for ease of
coding and readability. A comprehensive set of development
tools supports program development.
The functional block diagram
on page 1
shows the architec-
ture of the ADSP-219x core. It contains three independent
computational units: the ALU, the multiplier/accumulator
(MAC), and the shifter. The computational units process
16-bit data from the register file and have provisions to
support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs sin-
gle-cycle multiply, multiply/add, and multiply/subtract
operations. The MAC has two 40-bit accumulators, which
help with overflow. The shifter performs logical and arith-
metic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control, including multiword
and block floating-point representations.
Register-usage rules influence placement of input and
results within the computational units. For most operations,
the computational units’ data registers act as a data register
file, permitting any input or result register to provide input
to any unit for a computation. For feedback operations, the
computational units let the output (result) of any unit be
input to any unit on the next cycle. For conditional or mul-
tifunction instructions, there are restrictions on which data
registers may provide inputs or receive results from each
computational unit. For more information, see the
ADSP-219x DSP Instruction Set Reference.
A powerful program sequencer controls the flow of instruc-
tion execution. The sequencer supports conditional jumps,
subroutine calls, and low interrupt overhead. With internal
loop counters and loop stacks, the ADSP-2195 executes
looped code with zero overhead; no explicit jump instruc-
tions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
16-bit address pointers. Whenever the pointer is used to
access data (indirect addressing), it is pre- or post-modified
by the value of one of four possible modify registers. A length
value and base address may be associated with each pointer
to implement automatic modulo addressing for circular
buffers. Page registers in the DAGs allow circular addressing
REV. PrA
The ADSP-2195 DSP is a single-chip microcomputer
optimized for digital signal processing (DSP) and other high
speed numeric processing applications.
The ADSP-2195 combines the ADSP-219x family base
architecture (three computational units, two data address
generators, and a program sequencer) with three serial
ports, two SPI-compatible ports, one UART port, a DMA
controller, three programmable timers, general-purpose
Programmable Flag pins, extensive interrupt capabilities,
and on-chip program and data memory spaces.
The ADSP-2195 architecture is code-compatible with
ADSP-218x family DSPs. Although the architectures are
compatible, the ADSP-2195 architecture has a number of
enhancements over the ADSP-218x architecture. The
enhancements to computational units, data address gener-
ators, and program sequencer make the ADSP-2195 more
flexible and even easier to program than the
ADSP-218x DSPs.
Indirect addressing options provide addressing flexibility—
premodify with no update, pre- and post-modify by an
immediate 8-bit, two’s-complement value and base address
registers for easier implementation of circular buffering.
The ADSP-2195 integrates 48K words of on-chip memory
configured as 16K words (24-bit) of program RAM, 16K
words (16-bit) of data RAM, and 16K words (24-bit) of
program ROM. Power-down circuitry is also provided to
meet the low power needs of battery-operated portable
equipment. The ADSP-2195 is available in 144-lead LQFP
and mini-BGA packages.
Fabricated in a high-speed, low-power, CMOS process, the
ADSP-2195 operates with a 6.25 ns instruction cycle time
(160 MIPS). All instructions, except two multiword
instructions, can execute in a single DSP cycle.
The ADSP-2195’s flexible architecture and comprehensive
instruction set support multiple operations in parallel. For
example, in one processor cycle, the ADSP-2195 can:
•
•
•
•
•
Generate an address for the next instruction fetch
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
These operations take place while the processor
continues to:
• Receive and transmit data through two serial ports
• Receive and/or transmit data from a Host
• Receive or transmit data through the UART
4
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
35(/,0,1$5< 7(&+1,&$/ '$7$
September 2001
For current information contact Analog Devices at 800/262-5643
ADSP-2195
(;7(51$/
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within 64K word boundaries of each of the 256 memory
pages, but these buffers may not cross page boundaries.
Secondary registers duplicate all the primary registers in the
DAGs; switching between primary and secondary registers
provides a fast context switch.
Efficient data transfer in the core is achieved with the use of
internal buses:
•
•
•
•
•
•
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
DMA Address Bus
DMA Data Bus
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The two address buses (PMA and DMA) share a single
external address bus, allowing memory to be expanded
off-chip, and the two data buses (PMD and DMD) share a
single external data bus. Boot memory space and I/O
memory space also share the external buses.
Program memory can store both instructions and data, per-
mitting the ADSP-2195 to fetch two operands in a single
cycle, one from program memory and one from data
memory. The DSP’s dual memory buses also let the
ADSP-219x core fetch an operand from data memory and
the next instruction from program memory in a single cycle.
DSP Peripherals Architecture
The functional block diagram
on page 1
shows the DSP’s
on-chip peripherals, which include the external memory
interface, Host port, serial ports, SPI-compatible ports,
UART port, JTAG test and emulation port, timers, flags,
and interrupt controller. These on-chip peripherals can
connect to off-chip devices as shown in
Figure 1.
The ADSP-2195 has a 16-bit Host port with DMA capa-
bility that lets external Hosts access on-chip memory. This
24-pin parallel port consists of a 16-pin multiplexed
data/address bus and provides a low-service overhead data
move capability. Configurable for 8- or 16-bits, this port
provides a glueless interface to a wide variety of 8- and 16-bit
microcontrollers. Two chip-selects provide Hosts access to
the DSP’s entire memory map. The DSP is bootable
through this port.
The ADSP-2195 also has an external memory interface that
is shared by the DSP’s core, the DMA controller, and DMA
capable peripherals, which include the UART, SPORT0,
SPORT1, SPORT2, SPI0, SPI1, and the Host port. The
external port consists of a 16-bit data bus, a 22-bit address
bus, and control signals. The data bus is configurable to
provide an 8 or 16 bit interface to external memory. Support
for word packing lets the DSP access 16- or 24-bit words
from external memory regardless of the external data bus
width. When configured for an 8-bit interface, the unused
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Figure 1. ADSP-2195 System Diagram
eight lines provide eight programmable, bidirectional gen-
eral-purpose Programmable Flag lines, six of which can be
mapped to software condition signals.
The memory DMA controller lets the ADSP-2195 move
data and instructions from between memory spaces: inter-
nal-to-external, internal-to-internal, and external-to-
external. On-chip peripherals can also use this controller for
DMA transfers.
The ADSP-2195 can respond to up to seventeen interrupts
at any given time: three internal (stack, emulator kernel, and
power-down), two external (emulator and reset), and twelve
user-defined (peripherals) interrupts. Programmers assign
5
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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