HY5RS123235BFP
Revision History
Revision
No.
0.1
0.2
Defined target spec.
1. CAS Lantency(12~15) are removed.
2. CAS Latency(12~15) change to Reserved on page 11.
3. Additive Latency and Low Power Mode in EMRS are deleted
on page 16.
4. tCK_max changes from 3.3ns to 3ns.
tCK_max changes from 3ns to 3.3ns below CL10.
1. Added IDD Values
2. Changed Ordering Information with Power Supply
1. Changed tWR number at 1.2GHz speed on page 54
2. Changed typo for Ron on page 15
3. Added note.48 on page 53
1. Changed tRRD from 16 to 13 and tWTR from 8 to 10
at tCK=0.8
2. Inserted AC parameter value on 800MHz(tCK=1.2) for reference
on page 54
1. Changed tDH/S from 140ps to 130ps on 1GHz
2. Changed a VID(AC) value from 0.5/VDDQ+0.5 to 0.22/
VDDQ+0.3 (Min/Max) on page 46.
1. Changed PKG bottom mold on page 59.
2. Changed tRAS_max from 100K tCK to 70Kns on page 54.
3. Revised typo.
Revised Appendix C about the boundary sacn test on page 62.
1. Updated IDD6 value on page 47.
2. Inserted -18L instead of -2L and changed IDD value about that.
3. Revised the (-12)’s, (-1)’s and (-08)’s parameter value at table20 on
page 54.
1. Updated tFAW from 61 to 48 on page 54.
1. Inserted the thermal characteristics table on page 44.
Mar.2008
History
Draft Date
Apr. 2006
Jun. 2006
Remark
Preliminary
Preliminary
0.3
0.4
0.5
July. 2006
July. 2006
Aug. 2006
Preliminary
Preliminary
Preliminary
0.6
Sep. 2006
Preliminary
1.0
Oct. 2006
1.1
Oct. 2006
1.2
1.3
Nov. 2006
Apr. 2007
1.4
1.5
Rev. 1.5 / Apr. 2008
2
HY5RS123235BFP
DESCRIPTION
The Hynix HY5RS123235 is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits.
The Hynix HY5RS123235 is internally configured as a eight-bank DRAM.
The Hynix HY5RS123235 uses a double data rate architecture to achieve high-speed opreration. The double date rate architecture
is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the Hynix HY5RS123235 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM
core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the Hynix
HY5RS123235 is burst oriented; accesses start at a selected locations and continue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ of WRITE com-
mand. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed
(BA0,BA1, BA2 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command
are used to select the starting column location for the burst access. Prior to normal operation, the Hynix HY5RS123235 must be ini-
tialized.
FEATURES
•
2.05V/ 1.8V/ 1.5V power supply supports
(For more detail, Please see the Table 12 on page 43)
•
•
•
Single ended READ Strobe (RDQS) per byte
Single ended WRITE Strobe (WDQS) per byte
Internal, pipelined double-data-rate (DDR) architecture;
two data accesses per clock cycle
•
•
•
•
•
•
On Die Termination
Output Driver Strength adjustment by EMRS
Calibrated output driver
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
RDQS edge-aligned with data for READ; with WDQS
center-aligned with data for WRITE
•
8 internal banks for concurrent operation
•
•
•
•
•
•
•
•
•
•
•
•
•
CAS Latency: 4~11 (clock)
Data mask (DM) for masking WRITE data
4n prefetch
Programmable burst lengths: 4, 8
32ms, 8K-cycle auto refresh
Auto precharge option
Auto Refresh and Self Refresh Modes
1.8V Pseudo Open Drain I/O
Concurrent Auto Precharge support
tRAS lockout support, Active Termination support
Programmable Write latency(1, 2, 3, 4, 5, 6)
Boundary Scan Function with SEN pin
Mirror Function with MF pin
ORDERING INFORMATION
Part No.
HY5RS123235BFP-08
HY5RS123235BFP-1
HY5RS123235BFP-11
HY5RS123235BFP-14
HY5RS123235BFP-2
HY5RS123235BFP-14L
HY5RS123235BFP-18L
VDD/VDDQ=1.5V
VDD/VDDQ=1.8V
Power Supply
VDD/VDDQ=2.05V
Clock Frequency
1200MHz
1000MHz
900MHz
700MHz
500MHz
700MHz
550MHz
Max Data Rate
2400Mbps/pin
2000Mbps/pin
1800Mbps/pin
1400Mbps/pin
1000Mbps/pin
1400Mbps/pin
1100Mbps/pin
POD_15
POD_18
11mmx14mm
136Ball FBGA
Interface
Package
Note)
Above Hynix P/N’s and their homogeneous Subcomponents are RoHS (& Lead free) compliant
Rev. 1.5 / Apr. 2008
3