128Kx8 Bit High Speed Static RAM(3.3V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev No.
Rev. 0.0
Rev.1.0
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary.
Release to Final Data Sheet.
2.1. Delete Preliminary.
2.2. Delete 32-SOJ-300 package.
2.3. Add Capacitive load of the test environment in A.C test load.
2.4. Change D.C characteristics.
Previous spec.
Changed spec.
Items
(8/10/12ns part)
(8/10/12ns part)
I
CC
160/150/140mA
160/155/150mA
I
SB
30mA
50mA
Change Standby and Data Retention Current for L-ver.
Items
Previous spec.
Changed spec.
I
SB1
0.5mA
0.7mA
I
DR
at 3.0V
0.4mA
0.5mA
I
DR
at 2.0V
0.3mA
0.4mA
Draft Data
Apr. 1st, 1997
Jun. 1st, 1997
Remark
Design Target
Preliminary
Rev.2.0
Feb. 25th, 1998
Final
Rev. 2.1
Aug. 4th, 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.1
August 1998
KM68V1002B/BL, KM68V1002BI/BLI
128K x 8 Bit High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
• Fast Access Time 8,10,12ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 50mA(Max.)
(CMOS) : 5mA(Max.)
0.7mA(Max.) - L-Ver. only
Operating KM68V1002B/BL - 8 : 160mA(Max.)
KM68V1002B/BL - 10 : 155mA(Max.)
KM68V1002B/BL - 12 : 150mA(Max.)
• Single 3.3±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention ; L-Ver. only
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM68V1002BJ : 32-SOJ-400
KM68V1002BT : 32-TSOP2-400F
Preliminary
PRELIMINARY
CMOS SRAM
GENERAL DESCRIPTION
The KM68V1002B is a 1,048,576-bit high-speed Static Ran-
dom Access Memory organized as 131,072 words by 8 bits.
The KM68V1002B uses 8 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG′s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
high-density
high-speed
system
applications.
The
KM68V1002B is packaged in a 400mil 32-pin plastic SOJ or
TSOP2 forward.
ORDERING INFORMATION
KM68V1002B/BL -8/10/12
KM68V1002BI/BLI -8/10/12
Commercial Temp.
Industrial Temp.
PIN CONFIGURATION
(Top View)
A
0
A
1
1
2
3
4
5
6
7
8
9
32 A
16
31 A
15
30 A
14
29 A
13
28 OE
27 I/O
8
26 I/O
7
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
Pre-Charge Circuit
A
2
A
3
CS
I/O
1
I/O
2
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
Vcc
SOJ/
TSOP2
25 Vss
24 Vcc
23 I/O
6
22 I/O
5
21 A
12
20 A
11
19 A
10
18
17
A
9
A
8
Row Select
Vss
Memory Array
256 Rows
512x8 Columns
I/O
3
10
I/O
4
11
WE
A
4
A
5
12
13
14
15
16
I/O
1
~I/O
8
Data
Cont.
CLK
Gen.
I/O Circuit
Column Select
A
6
A
7
PIN FUNCTION
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
Pin Name
A
0
- A
16
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
No Connection
CS
WE
OE
WE
CS
OE
I/O
1
~ I/O
8
V
CC
V
SS
N.C
-2-
Rev 2.1
August 1998
KM68V1002B/BL, KM68V1002BI/BLI
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
T
A
Rating
-0.5 to 4.6
-0.5 to 4.6
1.0
-65 to 150
0 to 70
-40 to 85
Preliminary
PRELIMINARY
CMOS SRAM
Unit
V
V
W
°C
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3**
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3***
0.8
Unit
V
V
V
V
* The above parameters are also guaranteed at industrial temperature range.
** V
IL
(Min) = -2.0V a.c(Pulse Width
≤
6ns) for I
≤
20mA.
*** V
IH
(Max) = V
CC +
2.0V a.c (Pulse Width
≤
6ns) for I
≤
20mA.
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
Test Conditions
V
IN
= V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
= V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
= V
IH
or V
IL,
I
OUT
=0mA
Min. Cycle, CS=V
IH
f=0MHz, CS
≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
Normal
L-Ver.
8ns
10ns
12ns
Standby Current
I
SB
I
SB1
Min
-2
-2
-
-
-
-
-
-
-
2.4
Max
2
2
160
155
150
50
5
0.7
0.4
-
V
V
mA
mA
Unit
µA
µA
mA
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
6
Unit
pF
pF
-3-
Rev 2.1
August 1998
KM68V1002B/BL, KM68V1002BI/BLI
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
* The above test conditions are also applied at industrial temperature range.
Preliminary
PRELIMINARY
CMOS SRAM
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
R
L
= 50Ω
+3.3V
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
D
OUT
353Ω
319Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
Symbol
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
PU
t
PD
KM68V1002B/BL-8
Min
8
-
-
-
3
0
0
0
3
0
-
Max
-
8
8
4
-
-
4
4
-
-
8
KM68V1002B/BL-10
Min
10
-
-
-
3
0
0
0
3
0
-
Max
-
10
10
5
-
-
5
5
-
-
10
KM68V1002B/BL-12
Min
12
-
-
-
3
0
0
0
3
0
-
Max
-
12
12
6
-
-
6
6
-
-
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
-4-
Rev 2.1
August 1998
KM68V1002B/BL, KM68V1002BI/BLI
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
WR
t
WHZ
t
DW
t
DH
t
OW
KM68V1002B/BL-8
Min
8
6
0
6
6
8
0
0
4
0
3
Max
-
-
-
-
-
-
-
4
-
-
-
KM68V1002B/BL-10
Min
10
7
0
7
7
10
0
0
5
0
3
Max
-
-
-
-
-
-
-
5
-
-
-
Preliminary
PRELIMINARY
CMOS SRAM
KM68V1002B/BL-12
Min
12
8
0
8
8
12
0
0
6
0
3
Max
-
-
-
-
-
-
-
6
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
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