EEWORLDEEWORLDEEWORLD

Part Number

Search

CY7C460-15JC

Description
FIFO, 8KX9, 15ns, Asynchronous, CMOS, PQCC32, PLASTIC, LCC-32
Categorystorage    storage   
File Size413KB,13 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

CY7C460-15JC Overview

FIFO, 8KX9, 15ns, Asynchronous, CMOS, PQCC32, PLASTIC, LCC-32

CY7C460-15JC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCypress Semiconductor
Parts packaging codeQFJ
package instructionPLASTIC, LCC-32
Contacts32
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum access time15 ns
Other featuresRETRANSMIT
Maximum clock frequency (fCLK)33.3 MHz
period time30 ns
JESD-30 codeR-PQCC-J32
JESD-609 codee0
length13.97 mm
memory density73728 bit
Memory IC TypeOTHER FIFO
memory width9
Number of functions1
Number of terminals32
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize8KX9
Output characteristics3-STATE
ExportableNO
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC32,.5X.6
Package shapeRECTANGULAR
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height3.55 mm
Maximum standby current0.02 A
Maximum slew rate0.105 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width11.43 mm
This Material Copyrighted By Its Respective Manufacturer
A8 uses GPMC and FPGA to communicate, asynchronous page read mode configuration
[font=normal 宋体, Arial, Helvetica, sans-serif][color=#000000][size=12px]GPMC_CONFIG_1 to 7 are configured as follows[/size][/color][/font] [font=normal 宋体, Arial, Helvetica, sans-serif][color=#000000]...
zhoush DSP and ARM Processors
ZigBee frame structure
[align=left][color=rgb(63, 63, 63)][size=3] The design principle of the IEEE 802.15.4/ZigBee frame structure is to minimize the complexity of the network while ensuring that the network can transmit w...
Jacktang RF/Wirelessly
TVS tube array manufacturers
Which manufacturers are better at TVS tube arrays?...
bluestar09 Integrated technical exchanges
Guess the question, let's guess together
[i=s]This post was last edited by paulhyde on 2014-9-15 09:08[/i] :lol 09 Electronics Competition Question Guessing Group! Signal + Control Category! QQ No.: 89212186 Gather experts from various provi...
leo10202 Electronics Design Contest
"Aurora", WXEDA's first mid-to-high-end FPGA development board design launched
:) The code name of this development board is: [font=微软雅黑][size=5][color=red]Aurora Aurora[/color][/size][/font] [font=微软雅黑][size=4][backcolor=yellow][b]This is the first mid-to-high-end development b...
kdy FPGA/CPLD
How to mount jffs2 partition?
The Flash on my board is 32M, and 12M has been mounted in the Linux system, so there is 20M of space left. Now, because the space is not enough, I want to mount the remaining 20M space. Now the questi...
ljlixian1 Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2825  1345  508  610  2796  57  28  11  13  25 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号