CY7C1612KV18-333BZC datasheet, PDF

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CY7C1612KV18-333BZC: DescriptionQDR SRAM, 8MX18, 0.45ns, CMOS, PBGA165, FBGA-165; Categorystorage storage; File Size626KB，33 Pages; ManufacturerCypress Semiconductor

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CY7C1612KV18-333BZC Overview

QDR SRAM, 8MX18, 0.45ns, CMOS, PBGA165, FBGA-165

CY7C1612KV18-333BZC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Factory Lead Time	1 week
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	333 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	17 mm
memory density	150994944 bit
Memory IC Type	QDR SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	220
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum standby current	0.41 A
Minimum standby current	1.7 V
Maximum slew rate	0.97 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead/Silver (Sn/Pb/Ag)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	15 mm

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CY7C1625KV18

CY7C1612KV18

CY7C1614KV18

144-Mbit QDR

II SRAM Two-Word

Burst Architecture

144-Mbit QDR

II SRAM Two-Word Burst Architecture

Features

■

Configurations

CY7C1625KV18 – 16 M × 9

CY7C1612KV18 – 8 M × 18

CY7C1614KV18 – 4 M × 36

Separate independent read and write data ports

❐

Supports concurrent transactions

360-MHz clock for high bandwidth

Two-word burst on all accesses

Double data rate (DDR) interfaces on both read and write ports

(data transferred at 720 MHz) at 360 MHz

Two input clocks (K and K) for precise DDR timing

❐

SRAM uses rising edges only

Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

Single multiplexed address input bus latches address inputs

for both read and write ports

Separate port selects for depth expansion

Synchronous internally self-timed writes

Quad data rate (QDR

) II operates with 1.5-cycle read latency

when DOFF is asserted high

Operates similar to QDR I device with 1 cycle read latency when

DOFF is asserted low

Available in × 9, × 18, and × 36 configurations

Full data coherency, providing most current data

Core V

= 1.8 V (± 0.1 V); I/O V

DDQ

= 1.4 V to V

❐

Supports both 1.5 V and 1.8 V I/O supply

Available in 165-ball fine-pitch ball grid array (FBGA) package

(15 × 17 × 1.4 mm)

Offered in both Pb-free and non Pb-free packages

Variable drive high-speed transceiver logic (HSTL) output

buffers

JTAG 1149.1 compatible test access port

Phase Locked Loop (PLL) for accurate data placement

■

Functional Description

The CY7C1625KV18, CY7C1612KV18, and CY7C1614KV18

are 1.8-V synchronous pipelined SRAMs, equipped with QDR II

architecture. QDR II architecture consists of two separate ports:

the read port and the write port to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR II architecture has separate data inputs and

data outputs to completely eliminate the need to ‘turn around’ the

data bus that exists with common I/O devices. Access to each

port is through a common address bus. Addresses for read and

write addresses are latched on alternate rising edges of the input

(K) clock. Accesses to the QDR II read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with two 9-bit

words (CY7C1625KV18), 18-bit words (CY7C1612KV18), or

36-bit words (CY7C1614KV18) that burst sequentially into or out

of the device. Because data can be transferred into and out of

the device on every rising edge of both input clocks (K and K and

C and C), memory bandwidth is maximized while simplifying

system design by eliminating bus turnarounds.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

For a complete list of related documentation, click

here.

■

Selection Guide

Description

Maximum operating frequency

Maximum operating current

× 18

360 MHz

360

× 9 Not Offered

1025

× 36 Not Offered

333 MHz

333

950

970

1160

300 MHz

300

880

910

1080

250 MHz

250

780

800

950

Unit

MHz

Cypress Semiconductor Corporation

Document Number: 001-16238 Rev. *N

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised January 4, 2016

CY7C1612KV18-333BZC Related Products

	CY7C1612KV18-333BZC	CY7C1625KV18-333BZXC	CY7C1612KV18-250BZXC	CY7C1612KV18-300BZXC	CY7C1612KV18-360BZXC
Description	QDR SRAM, 8MX18, 0.45ns, CMOS, PBGA165, FBGA-165	QDR SRAM, 16MX9, 0.45ns, CMOS, PBGA165, FBGA-165	QDR SRAM, 8MX18, 0.45ns, CMOS, PBGA165, FBGA-165	QDR SRAM, 8MX18, 0.45ns, CMOS, PBGA165, 15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165	QDR SRAM, 8MX18, CMOS, PBGA165, FBGA-165
Is it Rohs certified?	incompatible	conform to	conform to	conform to	conform to
package instruction	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	LBGA, BGA165,11X15,40	15 X 17 MM, 1.40 MM HEIGHT, LEAD FREE, MO-216, FBGA-165	FBGA-165
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
JESD-30 code	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165	R-PBGA-B165
length	17 mm	17 mm	17 mm	17 mm	17 mm
memory density	150994944 bit	150994944 bit	150994944 bit	150994944 bit	150994944 bit
Memory IC Type	QDR SRAM	QDR SRAM	QDR SRAM	QDR SRAM	QDR SRAM
memory width	18	9	18	18	18
Number of functions	1	1	1	1	1
Number of terminals	165	165	165	165	165
word count	8388608 words	16777216 words	8388608 words	8388608 words	8388608 words
character code	8000000	16000000	8000000	8000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C
organize	8MX18	16MX9	8MX18	8MX18	8MX18
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA	LBGA	LBGA	LBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Maximum seat height	1.4 mm	1.4 mm	1.4 mm	1.4 mm	1.4 mm
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	15 mm	15 mm	15 mm	15 mm	15 mm
Maker	Cypress Semiconductor	-	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
Parts packaging code	BGA	BGA	BGA	BGA	-
Contacts	165	165	165	165	-
Factory Lead Time	1 week	-	1 week	1 week	1 week
Maximum access time	0.45 ns	0.45 ns	0.45 ns	0.45 ns	-
Other features	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	PIPELINED ARCHITECTURE	-
Maximum clock frequency (fCLK)	333 MHz	333 MHz	250 MHz	-	-
I/O type	SEPARATE	SEPARATE	SEPARATE	-	-
JESD-609 code	e0	e1	e1	e1	-
Output characteristics	3-STATE	3-STATE	3-STATE	-	-
Encapsulate equivalent code	BGA165,11X15,40	BGA165,11X15,40	BGA165,11X15,40	-	-
Peak Reflow Temperature (Celsius)	220	260	260	260	-
power supply	1.5/1.8,1.8 V	1.5/1.8,1.8 V	1.5/1.8,1.8 V	-	-
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-
Maximum standby current	0.41 A	0.41 A	0.37 A	-	-
Minimum standby current	1.7 V	1.7 V	1.7 V	-	-
Maximum slew rate	0.97 mA	0.95 mA	0.8 mA	-	-
Terminal surface	Tin/Lead/Silver (Sn/Pb/Ag)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	-
Maximum time at peak reflow temperature	30	40	40	40	-

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