D0600ANT1A datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> D0600ANT1A

D0600ANT1A: DescriptionMicroprocessor, 64-Bit, 600MHz, CMOS, PPGA462, STAGGERED, PGA-453; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，84 Pages; ManufacturerAMD; Websitehttp://www.amd.com

Download Datasheet Parametric View All

D0600ANT1A Overview

Microprocessor, 64-Bit, 600MHz, CMOS, PPGA462, STAGGERED, PGA-453

D0600ANT1A Parametric

Parameter Name	Attribute value
Maker	AMD
Parts packaging code	PGA
package instruction	IPGA,
Contacts	453
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	15
bit size	64
boundary scan	YES
maximum clock frequency	600 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	R-PPGA-P462
length	49.53 mm
low power mode	YES
Number of terminals	462
Package body material	PLASTIC/EPOXY
encapsulated code	IPGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, INTERSTITIAL PITCH
Certification status	Not Qualified
Maximum seat height	3.43 mm
speed	600 MHz
Nominal supply voltage	1.8 V
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	49.53 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

Preview

Download Datasheet

View All

Preliminary Information

AMD Duron

Processor

Data Sheet

Publication #

23802

Rev:

Issue Date:

June 2000

Preliminary Information

23802B—June 2000

AMD Duron™ Processor Data Sheet

Contents

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1

2.1

2.2

2.3

2.4

AMD Duron™ Processor Microarchitecture Summary . . . . . 2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

AMD System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1

Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Full-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Stop Grant and Sleep States. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Connection and Disconnection Protocol . . . . . . . . . . . . . . . . 11

Connection Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Connection State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2

Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10

6.11

6.12

6.13

Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 20

Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 20

SYSCLK and SYSCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 21

Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SYSCLK and SYSCLK# AC and DC Characteristics . . . . . . 23

AMD System Bus AC/DC Characteristics . . . . . . . . . . . . . . . 24

Push-Pull Mode IV Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

System Bus AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26

Southbridge AC and DC Characteristics . . . . . . . . . . . . . . . . 27

APIC Pin AC and DC Characteristics . . . . . . . . . . . . . . . . . . . 29

Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Signal Sequence and Timing Description . . . . . . . . . . . . . . . . 31

Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . . . . 34

Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . . 36

The AMD Duron Processor and Northbridge Reset Pins . . . 36

Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 31

7.1

7.2

Contents

iii

Preliminary Information

AMD Duron™ Processor Data Sheet

23802B—June 2000

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

8.1

8.2

8.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Socket Tabs for Heatsink Clips . . . . . . . . . . . . . . . . . . . . . . . 41

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMD System Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKIN, RSTCLK (SYSCLK) Pins . . . . . . . . . . . . . . . . . . . . . .

CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . . .

DBRDY and DBREQ# Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .

FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INTR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

K7CLKOUT and K7CLKOUT# Pins . . . . . . . . . . . . . . . . . . . .

Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SADDIN[1]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . . . . .

Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCHECK[7:0]# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STPCLK# Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SYSCLK and SYSCLK# Pins . . . . . . . . . . . . . . . . . . . . . . . . . .

SYSVREFMODE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VCCA Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VREFSYS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ZN, VCC_Z, ZP, and VSS_Z Pins . . . . . . . . . . . . . . . . . . . . . . .

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

9.1

9.2

9.3

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Standard AMD Duron Processor Products. . . . . . . . . . . . . . . . . . . . . 67

Appendix A Conventions, Abbreviations, and References . . . . . . . . . . . . . . . . . . . . .69

Contents

Recommended Resources

Homemade standard signal transmitter

High speed integrator circuit diagram

Musical doorbell circuit that can identify visitors

Infrared microscope circuit

transistor voltage regulator

820e computer motherboard circuit diagram_33

Hiring embedded software engineer: Headhunter position [Shenzhen] Job responsibilities: 1. Participate in the development of new products, understand hardware design, schematic design, PCB Layout, and solve hardware-related problems in...; ff318421749 Recruitment

Innocent burglar alarms make people happy and worried: When I first bought my car, I treasured it so much that I bought a big lock that looked like a spear and locked it on the clutch and steering wheel. I was still not satisfied and wanted to install an ...; 幸福的娃 Industrial Control Electronics

Friends recommend a circuit simulation software: Electronic Engineer Technical Exchange (12425841)...; 杨华& PCB Design

Definition and function of the middle segment in DSP program: The target file generated by TI's compiler is a modular ELF format file. Code and data are organized in the form of segments in the ELF file. An ELF segment occupies a continuous block of code or data...; 火辣西米秀 DSP and ARM Processors

Are there many tourists in Guangzhou and Shenzhen during the Chinese New Year?: Are there many tourists in Guangzhou and Shenzhen during the Chinese New Year?...; 蓝雨夜 Talking

Ask about wince5.0 system customization: When customizing wince5.0, I read some materials and found the following content: (1) Merge configuration files: All .BIB files are merged into CE.BIB. CE.BIB contains all files in the image NK.BIN; a...; ltiqc Embedded System

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components