D0550ANR2B datasheet, PDF - EEWORLD Datasheet

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D0550ANR2B: DescriptionMicroprocessor, 64-Bit, 550MHz, CMOS, CPGA462, STAGGERED, PGA-453; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，84 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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D0550ANR2B Overview

Microprocessor, 64-Bit, 550MHz, CMOS, CPGA462, STAGGERED, PGA-453

D0550ANR2B Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	AMD
Parts packaging code	PGA
package instruction	IPGA, SPGA462,37X37
Contacts	453
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	15
bit size	64
boundary scan	YES
maximum clock frequency	550 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	R-CPGA-P462
JESD-609 code	e0
length	49.53 mm
low power mode	YES
Number of terminals	462
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	IPGA
Encapsulate equivalent code	SPGA462,37X37
Package shape	RECTANGULAR
Package form	GRID ARRAY, INTERSTITIAL PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8,2.5 V
Certification status	Not Qualified
Maximum seat height	3.43 mm
speed	550 MHz
Maximum slew rate	15800 mA
Nominal supply voltage	1.8 V
surface mount	NO
technology	CMOS
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Maximum time at peak reflow temperature	NOT SPECIFIED
width	49.53 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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Preliminary Information

AMD Duron

Processor

Data Sheet

Publication #

23802

Rev:

Issue Date:

June 2000

Preliminary Information

23802B—June 2000

AMD Duron™ Processor Data Sheet

Contents

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1

2.1

2.2

2.3

2.4

AMD Duron™ Processor Microarchitecture Summary . . . . . 2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

AMD System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1

Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Full-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Stop Grant and Sleep States. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Connection and Disconnection Protocol . . . . . . . . . . . . . . . . 11

Connection Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Connection State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.2

Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

6.10

6.11

6.12

6.13

Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 20

Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 20

SYSCLK and SYSCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 21

Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

SYSCLK and SYSCLK# AC and DC Characteristics . . . . . . 23

AMD System Bus AC/DC Characteristics . . . . . . . . . . . . . . . 24

Push-Pull Mode IV Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

System Bus AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26

Southbridge AC and DC Characteristics . . . . . . . . . . . . . . . . 27

APIC Pin AC and DC Characteristics . . . . . . . . . . . . . . . . . . . 29

Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Signal Sequence and Timing Description . . . . . . . . . . . . . . . . 31

Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . . . . 34

Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . . 36

The AMD Duron Processor and Northbridge Reset Pins . . . 36

Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 31

7.1

7.2

Contents

iii

Preliminary Information

AMD Duron™ Processor Data Sheet

23802B—June 2000

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

8.1

8.2

8.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Socket Tabs for Heatsink Clips . . . . . . . . . . . . . . . . . . . . . . . 41

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMD System Bus Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKIN, RSTCLK (SYSCLK) Pins . . . . . . . . . . . . . . . . . . . . . .

CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . . .

DBRDY and DBREQ# Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .

FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INTR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

K7CLKOUT and K7CLKOUT# Pins . . . . . . . . . . . . . . . . . . . .

Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SADDIN[1]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . . . . .

Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCHECK[7:0]# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STPCLK# Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SYSCLK and SYSCLK# Pins . . . . . . . . . . . . . . . . . . . . . . . . . .

SYSVREFMODE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VCCA Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VREFSYS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ZN, VCC_Z, ZP, and VSS_Z Pins . . . . . . . . . . . . . . . . . . . . . . .

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

9.1

9.2

9.3

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Standard AMD Duron Processor Products. . . . . . . . . . . . . . . . . . . . . 67

Appendix A Conventions, Abbreviations, and References . . . . . . . . . . . . . . . . . . . . .69

Contents

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