CY14B256L-SZ25XCT datasheet, PDF

Datasheet> All Categories > storage> storage> CY14B256L-SZ25XCT

CY14B256L-SZ25XCT: DescriptionNon-Volatile SRAM, 32KX8, 25ns, CMOS, PDSO32, 0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-32; Categorystorage storage; File Size530KB，18 Pages; ManufacturerCypress Semiconductor; Environmental Compliance

Download Datasheet Parametric Compare View All

CY14B256L-SZ25XCT Overview

Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDSO32, 0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-32

CY14B256L-SZ25XCT Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Cypress Semiconductor
Parts packaging code	SOIC
package instruction	0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-32
Contacts	32
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	25 ns
JESD-30 code	R-PDSO-G32
JESD-609 code	e3
length	20.726 mm
memory density	262144 bit
Memory IC Type	NON-VOLATILE SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	32
word count	32768 words
character code	32000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP32,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3/3.3 V
Certification status	Not Qualified
Maximum seat height	2.54 mm
Maximum standby current	0.003 A
Maximum slew rate	0.065 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	7.5057 mm

CY14B256L-SZ25XCT Preview

CY14B256L

256 Kbit (32K x 8) nvSRAM

Features

■

Functional Description

The Cypress CY14B256L is a fast static RAM with a nonvolatile

element in each memory cell. The embedded nonvolatile

elements incorporate QuantumTrap technology producing the

world’s most reliable nonvolatile memory. The SRAM provides

unlimited read and write cycles, while independent, nonvolatile

data resides in the highly reliable QuantumTrap cell. Data

transfers from the SRAM to the nonvolatile elements (the

STORE operation) takes place automatically at power down. On

power up, data is restored to the SRAM (the RECALL operation)

from the nonvolatile memory. Both the STORE and RECALL

operations are also available under software control. A hardware

STORE is initiated with the HSB pin.

25 ns, 35 ns, and 45 ns access times

Pin compatible with STK14D88

Hands off automatic STORE on power down with only a small

capacitor

STORE to QuantumTrap™ nonvolatile elements is initiated by

software, hardware, or AutoStore™ on power down

RECALL to SRAM initiated by software or power up

Unlimited READ, WRITE, and RECALL cycles

200,000 STORE cycles to QuantumTrap

20 year data retention at 55°C

Single 3V +20%, –10% operation

Commercial and industrial temperature

32-pin (300 mil) SOIC and 48-pin (300 mil) SSOP packages

RoHS compliance

Logic Block Diagram

Quantum Trap

512 X 512

CAP

STORE

POWER

CONTROL

STORE/

RECALL

CONTROL

ROW DECODER

STATIC RAM

ARRAY

512 X 512

RECALL

HSB

SOFTWARE

DETECT

COLUMN I/O

INPUT BUFFERS

COLUMN DEC

Cypress Semiconductor Corporation

Document Number: 001-06422 Rev. *H

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised January 30, 2009

[+] Feedback

CY14B256L

Pin Configurations

Figure 1. Pin Diagram - 32-Pin SOIC and 48-Pin SSOP

Pin Definitions

Pin Name

–A

-DQ

HSB

Alt

IO Type

Input

Ground

Description

Address Inputs.

Used to select one of the 32,768 bytes of the nvSRAM.

Write Enable Input, Active LOW.

When the chip is enabled and WE is LOW, data on the IO

pins is written to the specific address location.

Chip Enable Input, Active LOW.

When LOW, selects the chip. When HIGH, deselects the chip.

Output Enable, Active LOW.

The active LOW OE input enables the data output buffers during

read cycles. Deasserting OE HIGH causes the IO pins to tri-state.

Ground for the Device.

The device is connected to ground of the system.

Input or Output

Bidirectional Data IO Lines.

Used as input or output lines depending on operation.

Power Supply

Power Supply Inputs to the Device.

Input or Output

Hardware Store Busy (HSB).

When LOW, this output indicates a Hardware Store is in progress.

When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal

pull up resistor keeps this pin high if not connected (connection optional).

Power Supply

AutoStore Capacitor.

Supplies power to nvSRAM during power loss to store data from SRAM

to nonvolatile elements.

No Connect

No Connect.

This pin is not connected to the die.

CAP

Document Number: 001-06422 Rev. *H

Page 2 of 18

[+] Feedback

CY14B256L

Device Operation

The CY14B256L nvSRAM is made up of two functional compo-

nents paired in the same physical cell. These are an SRAM

memory cell and a nonvolatile QuantumTrap cell. The SRAM

memory cell operates as a standard fast static RAM. Data in the

SRAM is transferred to the nonvolatile cell (the STORE

operation) or from the nonvolatile cell to SRAM (the RECALL

operation). This unique architecture enables the storage and

recall of all cells in parallel. During the STORE and RECALL

operations, SRAM READ and WRITE operations are inhibited.

The CY14B256L supports unlimited reads and writes similar to

a typical SRAM. In addition, it provides unlimited RECALL opera-

tions from the nonvolatile cells and up to 200K STORE opera-

tions.

the V

CAP

pin is driven to 5V by a charge pump internal to the chip.

A pull up is placed on WE to hold it inactive during power up.

Figure 2. AutoStore Mode

CAP

10k Ohm

SRAM Read

The CY14B256L performs a READ cycle whenever CE and OE

are LOW while WE and HSB are HIGH. The address specified

on pins A

0–14

determines the 32,768 data bytes accessed. When

the READ is initiated by an address transition, the outputs are

valid after a delay of t

(READ cycle 1). If the READ is initiated

by CE or OE, the outputs are valid at t

ACE

or at t

DOE

, whichever

is later (READ cycle 2). The data outputs repeatedly respond to

address changes within the t

access time without the need for

transitions on any control input pins, and remains valid until

another address change or until CE or OE is brought HIGH, or

WE or HSB is brought LOW.

SRAM Write

A WRITE cycle is performed whenever CE and WE are LOW and

HSB is HIGH. The address inputs must be stable prior to entering

the WRITE cycle and must remain stable until either CE or WE

goes HIGH at the end of the cycle. The data on the common IO

pins DQ

0–7

are written into the memory if it has valid t

, before

the end of a WE controlled WRITE or before the end of an CE

controlled WRITE. Keep OE HIGH during the entire WRITE cycle

to avoid data bus contention on common IO lines. If OE is left

LOW, internal circuitry turns off the output buffers t

HZWE

after WE

goes LOW.

To reduce unnecessary nonvolatile stores, AutoStore and

Hardware Store operations are ignored, unless at least one

WRITE operation has taken place since the most recent STORE

or RECALL cycle. Software initiated STORE cycles are

performed regardless of whether a WRITE operation has taken

place. An optional pull-up resistor is shown connected to HSB.

The HSB signal is monitored by the system to detect if an

AutoStore cycle is in progress.

Hardware STORE (HSB) Operation

The CY14B256L provides the HSB pin for controlling and

acknowledging the STORE operations. The HSB pin is used to

request a hardware STORE cycle. When the HSB pin is driven

LOW, the CY14B256L conditionally initiates a STORE operation

after t

DELAY

. An actual STORE cycle only begins if a WRITE to

the SRAM takes place since the last STORE or RECALL cycle.

The HSB pin also acts as an open drain driver that is internally

driven LOW to indicate a busy condition, while the STORE

(initiated by any means) is in progress.

SRAM READ and WRITE operations, that are in progress when

HSB is driven LOW by any means, are given time to complete

before the STORE operation is initiated. After HSB goes LOW,

the CY14B256L continues SRAM operations for t

DELAY

. During

DELAY

, multiple SRAM READ operations take place. If a WRITE

is in progress when HSB is pulled LOW, it allows a time, t

DELAY

to complete. However, any SRAM WRITE cycles requested after

HSB goes LOW are inhibited until HSB returns HIGH.

If HSB is not used, it is left unconnected.

AutoStore Operation

The CY14B256L stores data to nvSRAM using one of three

storage operations:

1. Hardware store activated by HSB

2. Software store activated by an address sequence

3. AutoStore on device power down

AutoStore operation is a unique feature of QuantumTrap

technology and is enabled by default on the CY14B256L.

During normal operation, the device draws current from V

charge a capacitor connected to the V

CAP

pin. This stored

charge is used by the chip to perform a single STORE operation.

If the voltage on the V

pin drops below V

SWITCH

, the part

automatically disconnects the V

CAP

pin from V

. A STORE

operation is initiated with power provided by the V

CAP

capacitor.

Figure 2

shows the proper connection of the storage capacitor

CAP

) for automatic store operation. Refer to the

DC Electrical

Characteristics

on page 7 for the size of V

CAP

. The voltage on

Document Number: 001-06422 Rev. *H

Hardware RECALL (Power Up)

During power up or after any low power condition (V

SWITCH

), an internal RECALL request is latched. When V

Page 3 of 18

0.1

[+] Feedback

CY14B256L

once again exceeds the sense voltage of V

SWITCH

, a RECALL

cycle is automatically initiated and takes t

HRECALL

to complete.

Data Protection

The CY14B256L protects data from corruption during low

voltage conditions by inhibiting all externally initiated STORE

and WRITE operations. The low voltage condition is detected

when V

is less than V

SWITCH

. If the CY14B256L is in a WRITE

mode (both CE and WE are low) at power up after a RECALL or

after a STORE, the WRITE is inhibited until a negative transition

on CE or WE is detected. This protects against inadvertent writes

during power up or brown out conditions.

Software STORE

Data is transferred from the SRAM to the nonvolatile memory by

a software address sequence. The CY14B256L software

STORE cycle is initiated by executing sequential CE controlled

READ cycles from six specific address locations in exact order.

During the STORE cycle, an erase of the previous nonvolatile

data is first performed followed by a program of the nonvolatile

elements. When a STORE cycle is initiated, input and output are

disabled until the cycle is completed.

Because a sequence of READs from specific addresses is used

for STORE initiation, it is important that no other READ or WRITE

accesses intervene in the sequence. If they intervene, the

sequence is aborted and no STORE or RECALL takes place.

To initiate the software STORE cycle, the following READ

sequence is performed:

1. Read address 0x0E38, Valid READ

2. Read address 0x31C7, Valid READ

3. Read address 0x03E0, Valid READ

4. Read address 0x3C1F, Valid READ

5. Read address 0x303F, Valid READ

6. Read address 0x0FC0, Initiate STORE cycle

The software sequence is clocked with CE controlled READs or

OE controlled READs. When the sixth address in the sequence

is entered, the STORE cycle commences and the chip is

disabled. It is important that READ cycles and not WRITE cycles

are used in the sequence. It is not necessary that OE is LOW for

a valid sequence. After the t

STORE

cycle time is fulfilled, the

SRAM is again activated for READ and WRITE operation.

Noise Considerations

The CY14B256L is a high speed memory. It must have a high

frequency bypass capacitor of approximately 0.1 µF connected

between V

and V

SS,

using leads and traces that are as short

as possible. As with all high speed CMOS ICs, careful routing of

power, ground, and signals reduce circuit noise.

Low Average Active Power

CMOS technology provides the CY14B256L the benefit of

drawing significantly less current when it is cycled at times longer

than 50 ns.

Figure 3

shows the relationship between I

and

READ or WRITE cycle time. Worst case current consumption is

shown for both CMOS and TTL input levels (commercial temper-

ature range, VCC = 3.6V, 100% duty cycle on chip enable). Only

standby current is drawn when the chip is disabled. The overall

average current drawn by the CY14B256L depends on the

following items:

■

The duty cycle of chip enable

The overall cycle rate for accesses

The ratio of READs to WRITEs

CMOS versus TTL input levels

The operating temperature

The V

level

IO loading

Software RECALL

Data is transferred from the nonvolatile memory to the SRAM by

a software address sequence. A software RECALL cycle is

initiated with a sequence of READ operations in a manner similar

to the software STORE initiation. To initiate the RECALL cycle,

the following sequence of CE controlled READ operations is

performed:

1. Read address 0x0E38, Valid READ

2. Read address 0x31C7, Valid READ

3. Read address 0x03E0, Valid READ

4. Read address 0x3C1F, Valid READ

5. Read address 0x303F, Valid READ

6. Read address 0x0C63, Initiate RECALL cycle

Internally, RECALL is a two step procedure. First, the SRAM data

is cleared, and then the nonvolatile information is transferred into

the SRAM cells. After the t

RECALL

cycle time, the SRAM is once

again ready for READ and WRITE operations. The RECALL

operation does not alter the data in the nonvolatile elements. The

nonvolatile data can be recalled an unlimited number of times.

■

Figure 3. Current vs. Cycle Time

Document Number: 001-06422 Rev. *H

Page 4 of 18

[+] Feedback

CY14B256L

Preventing Store

Disable the AutoStore function by initiating an AutoStore Disable

sequence. A sequence of READ operations is performed in a

manner similar to the software STORE initiation. To initiate the

AutoStore Disable sequence, perform the following sequence of

CE controlled or OE controlled READ operations:

1. Read Address 0x0E38 Valid READ

2. Read Address 0x31C7 Valid READ

3. Read Address 0x03E0 Valid READ

4. Read Address 0x3C1F Valid READ

5. Read Address 0x303F Valid READ

6. Read Address 0x03F8 AutoStore Disable

Re-enable the AutoStore by initiating an AutoStore Enable

sequence. A sequence of READ operations is performed in a

manner similar to the software RECALL initiation. To initiate the

AutoStore Enable sequence, perform the following sequence of

CE controlled or OE controlled READ operations:

1. Read Address 0x0E38 Valid READ

2. Read Address 0x31C7 Valid READ

3. Read Address 0x03E0 Valid READ

4. Read Address 0x3C1F Valid READ

5. Read Address 0x303F Valid READ

6. Read Address 0x07F0 AutoStore Enable

If the AutoStore function is disabled or re-enabled, a manual

STORE operation (Hardware or Software) is issued to save the

AutoStore state through subsequent power down cycles. The

part comes from the factory with AutoStore enabled.

■

Best Practices

nvSRAM products have been used effectively for over 15 years.

While ease of use is one of the product’s main system values,

experience gained working with hundreds of applications has

resulted in the following suggestions as best practices:

■

The nonvolatile cells in an nvSRAM are programmed on the

test floor during final test and quality assurance. Incoming

inspection routines at customer or contract manufacturer’s

sites sometimes reprogram these values. Final NV patterns are

typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End

product’s firmware should not assume an NV array is in a set

programmed state. Routines that check memory content

values to determine first time system configuration, cold or

warm boot status, and so on should always program a unique

NV pattern (for example, complex 4-byte pattern of 46 E6 49

53 hex or more random bytes) as part of the final system

manufacturing test to ensure these system routines work

consistently.

Power up boot firmware routines should rewrite the nvSRAM

into the desired state. While the nvSRAM is shipped in a preset

state, the best practice is to again rewrite the nvSRAM into the

desired state as a safeguard against events that might flip the

bit inadvertently (program bugs, incoming inspection routines,

and so on).

If autostore is firmware disabled, it does not reset to “autostore

enabled” on every power down event captured by the nvSRAM.

The application firmware should re-enable or re-disable

autostore on each reset sequence based on the behavior

desired.

The V

CAP

value specified in this data sheet includes a minimum

and a maximum value size. Best practice is to meet this

requirement and not exceed the maximum V

CAP

value because

higher inrush currents may reduce the reliability of the internal

pass transistor. Customers that want to use a larger V

CAP

value

to make sure there is extra store charge should discuss their

CAP

size selection with Cypress to understand any impact on

the V

CAP

voltage level at the end of a t

RECALL

period.

■

Document Number: 001-06422 Rev. *H

Page 5 of 18

[+] Feedback

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

CY14B256L-SZ25XCT Related Products

	CY14B256L-SZ25XCT	CY14B256L-SP25XIT	CY14B256L-SP25XC	CY14B256L-SZ25XC	CY14B256L-SZ25XIT
Description	Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDSO32, 0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-32	Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDSO48, 0.300 INCH, ROHS COMPLIANT, SSOP-48	Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDSO48, 0.300 INCH, ROHS COMPLIANT, SSOP-48	Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDSO32, 0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-32	Non-Volatile SRAM, 32KX8, 25ns, CMOS, PDSO32, 0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-32
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
Maker	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor	Cypress Semiconductor
Parts packaging code	SOIC	SSOP	SSOP	SOIC	SOIC
package instruction	0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-32	0.300 INCH, ROHS COMPLIANT, SSOP-48	0.300 INCH, ROHS COMPLIANT, SSOP-48	0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-32	0.300 INCH, ROHS COMPLIANT, MO-119, SOIC-32
Contacts	32	48	48	32	32
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99
Maximum access time	25 ns	25 ns	25 ns	25 ns	25 ns
JESD-30 code	R-PDSO-G32	R-PDSO-G48	R-PDSO-G48	R-PDSO-G32	R-PDSO-G32
JESD-609 code	e3	e4	e4	e3	e3
length	20.726 mm	15.875 mm	15.875 mm	20.726 mm	20.726 mm
memory density	262144 bit	262144 bit	262144 bit	262144 bit	262144 bit
Memory IC Type	NON-VOLATILE SRAM	NON-VOLATILE SRAM	NON-VOLATILE SRAM	NON-VOLATILE SRAM	NON-VOLATILE SRAM
memory width	8	8	8	8	8
Humidity sensitivity level	3	3	3	3	3
Number of functions	1	1	1	1	1
Number of terminals	32	48	48	32	32
word count	32768 words	32768 words	32768 words	32768 words	32768 words
character code	32000	32000	32000	32000	32000
Operating mode	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS	ASYNCHRONOUS
Maximum operating temperature	70 °C	85 °C	70 °C	70 °C	85 °C
organize	32KX8	32KX8	32KX8	32KX8	32KX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SSOP	SSOP	SOP	SOP
Encapsulate equivalent code	SOP32,.4	SSOP48,.4	SSOP48,.4	SOP32,.4	SOP32,.4
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	260	260	260
power supply	3/3.3 V	3/3.3 V	3/3.3 V	3/3.3 V	3/3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.54 mm	2.794 mm	2.794 mm	2.54 mm	2.54 mm
Maximum standby current	0.003 A	0.003 A	0.003 A	0.003 A	0.003 A
Maximum slew rate	0.065 mA	0.07 mA	0.065 mA	0.065 mA	0.07 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.635 mm	0.635 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	20	20	20	20	20
width	7.5057 mm	7.5057 mm	7.5057 mm	7.5057 mm	7.5057 mm

Recommended Resources

Switching power supply starting circuit diagram using triode

Negative voltage output switching regulator circuit diagram

Using photoelectric thyristor as overvoltage protection circuit

MPY100 voltage divider - functional block diagram

Temperature automatic control circuit

Differential Line Driver

A bug that is easily overlooked in the program: Requirement: When a button is pressed, the action to be completed is executed. When the action is completed, if the button is still pressed, the original repeated action will not be executed. That is ...; zhangxian8031 Embedded System

Appendix A - Instrumentation Amplifier Specifications: Appendix A - Instrumentation Amplifier Specifications...; 安_然 Analogue and Mixed Signal

Is there any mobile phone positioning software that you would recommend?: It is a software that can know the location with a mobile phone number...; 刘小天 Talking

Let’s run together, don’t be afraid!: It is said that if you stick to it for 21 days, you can develop a habit! I started running on July 29th. I want to run for 21 days and develop a good habit of exercising! Day 1: I ran two laps at inte...; chenzhufly Talking

Unable to completely erase nor flash sector in uboot: Today I used uboot1.14 to debug spansion's S29GL064MR4 nor flash. I used the CFI interface driver that comes with uboot. It can identify the size of the flash, manufacturer ID and other information, a...; jbcfelix Embedded System

Seeking 3G HSUPA wireless network card solution: The company is in urgent need of 3G HSUPA wireless network card solutions or products, please contact: 13798521741 Mr. Li [email=.li2006rui@163.com].li2006rui@163.com[/email] [url=http://www.rdeasy.cn...; rdeasy RF/Wirelessly

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components