ATSAML10E16A-AUTKPH datasheet, PDF

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ATSAML10E16A-AUTKPH: DescriptionRISC Microcontroller; CategoryThe embedded processor and controller Microcontrollers and processors; File Size9MB，1222 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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ATSAML10E16A-AUTKPH Overview

RISC Microcontroller

ATSAML10E16A-AUTKPH Parametric

Parameter Name	Attribute value
Maker	Microchip
package instruction	TQFP-32
Reach Compliance Code	compliant
Has ADC	YES
Address bus width
bit size	32
maximum clock frequency	32 MHz
DAC channel	YES
DMA channel	YES
External data bus width
JESD-30 code	S-PQFP-G32
length	7 mm
Number of I/O lines	25
Number of terminals	32
On-chip program ROM width	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	TQFP
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE
ROM programmability	FLASH
Filter level	TS 16949
Maximum seat height	1.2 mm
speed	32 MHz
Maximum supply voltage	1.2 V
Minimum supply voltage	0.9 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
width	7 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

ATSAML10E16A-AUTKPH Preview

SAM L10/L11 Family

Ultra Low-Power, 32-bit Cortex-M23 MCUs with TrustZone,

Crypto, and Enhanced PTC

Features

•

Operating Conditions:

1.62V to 3.63V, -40ºC to +125ºC, DC to 32 MHz

•

Core:

32 MHz (2.64 CoreMark/MHz and up to 31 DMIPS) Arm

Cortex

-M23 with:

– Single-cycle hardware multiplier

– Hardware divider

– Nested Vector Interrupt Controller (NVIC)

– Memory Protection Unit (MPU)

– Stack Limit Checking

– TrustZone

for ARMv8-M (optional)

•

System

– Power-on Reset (POR) and programmable Brown-out Detection (BOD)

– 8-channel Direct Memory Access Controller (DMAC)

– 8-channel event system for Inter-peripheral Core-independent Operation

– CRC-32 generator

•

Memory

– 64/32/16 KB Flash

– 16/8/4 KB SRAM

– 2 KB Data Flash Write-While-Read (WWR) section for non-volatile data storage

– 256 bytes TrustRAM with physical protection features

•

Clock Management

– Flexible clock distribution optimized for low power

– 32.768 kHz crystal oscillator

– 32.768 kHz ultra low-power internal RC oscillator

–

0.4 to 32 MHz crystal oscillator

16/12/8/4 MHz low-power internal RC oscillator

Ultra low-power digital Frequency-Locked Loop (DFLLULP)

32-96 MHz fractional digital Phase-Locked Loop (FDPLL96M)

One frequency meter

•

Low-Power and Power Management

– Active, Idle, Standby with partial or full SRAM retention and off sleep modes:

• Active mode (< 25 μA/MHz)

• Idle mode (< 10 μA/MHz) with 1.5 μs wake-up time

2019 Microchip Technology Inc.

Datasheet

DS60001513D-page 1

SAM L10/L11 Family

• Standby with Full SRAM Retention (0.5 μA) with 5.3 μs wake-up time

• Off mode (< 100 nA)

Static and dynamic power gating architecture

Sleepwalking peripherals

Two performance levels

Embedded Buck/LDO regulator with on-the-fly selection

–

•

Security

– Up to four tamper pins for static and dynamic intrusion detections

– Data Flash

• Optimized for secrets storage

• Address and Data Scrambling with user-defined key (optional)

• Rapid Tamper erase on scrambling key and on one user-defined row

• Silent access for side channel attack resistance

– TrustRAM

• Address and Data scrambling with user-defined key

• Chip-level tamper detection on physical RAM to resist microprobing attacks

• Rapid Tamper Erase on scrambling key and RAM data

• Silent access for side channel attack resistance

• Data remanence prevention

– Peripherals

• One True Random Generator (TRNG)

• AES-128, SHA-256, and GCM cryptography accelerators (optional)

• Secure pin multiplexing to isolate on dedicated I/O pins a secured communication with

external devices from the non-secure application (optional)

– TrustZone for flexible hardware isolation of memories and peripherals (optional)

• Up to six regions for the Flash

• Up to two regions for the Data Flash

• Up to two regions for the SRAM

• Individual security attribution for each peripheral, I/O, external interrupt line, and Event

System Channel

– Secure Boot with SHA-based authentication (optional)

– Up to three debug access levels

– Up to three Chip Erase commands to erase part of or the entire embedded memories

– Unique 128-bit serial number

– SAM L11 Securely Key Provisioned (KPH) (optional)

• Key Provisioning using Root of Trust flow

• Security Software Framework using Kinibi-M

™

Software Development Kit (SDK)

•

Advanced Analog and Touch

– One 12-bit 1 Msps Analog-to-Digital Converter (ADC) with up to 10 channels

– Two Analog Comparators (AC) with window compare function

– One 10-bit 350 kSPS Digital-to-Analog Converter (DAC) with external and internal outputs

– Three Operational Amplifiers (OPAMP)

2019 Microchip Technology Inc.

Datasheet

DS60001513D-page 2

SAM L10/L11 Family

– One enhanced Peripheral Touch Controller (PTC):

• Up to 20 self-capacitance channels

• Up to 100 (10 x 10) mutual-capacitance channels

• Low-power, high-sensitivity, environmentally robust capacitive touch buttons, sliders, and

wheels

• Hardware noise filtering and noise signal desynchronization for high conducted immunity

• Driven Shield Plus for better noise immunity and moisture tolerance

• Parallel Acquisition through Polarity control

• Supports wake-up on touch from Standby Sleep mode

•

Communication Interfaces

– Up to three Serial Communication Interfaces (SERCOM) that can operate as:

• USART with full-duplex and single-wire half-duplex configuration

• I

C up to 3.4 Mbit/s (High-Speed mode) on one instance and up to 1 Mbit/s (Fast-mode

Plus) on the second instance

•

Serial Peripheral Interface (SPI)

ISO7816 on one instance

RS-485 on one instance

LIN Slave on one instance

•

Timers/Output Compare/Input Capture

– Three 16-bit Timers/Counters (TC), each configurable as:

• One 16-bit TC with two compare/capture channels

• One 8-bit TC with two compare/capture channels

• One 32-bit TC with two compare/capture channels, by using two TCs

– 32-bit Real-Time Counter (RTC) with clock/calendar functions

– Watchdog Timer (WDT) with Window mode

•

Input/Output (I/O)

– Up to 25 programmable I/O lines

– Eight external interrupts (EIC)

– One non-maskable interrupt (NMI)

– One Configurable Custom Logic (CCL) that supports:

• Combinatorial logic functions, such as AND, NAND, OR, and NOR

• Sequential logic functions, such as Flip-Flop and Latches

•

Qualification and Class-B Support

– AEC-Q100 REVH (Grade 1 [-40ºC to +125ºC]) (planned)

– Class-B safety library, IEC 60730 (future)

•

Debugger Development Support

– Two-pin Serial Wire Debug (SWD) programming and debugging interface

•

Packages

Type

Pin Count

I/O Pins (up to)

VQFN

TQFP

SSOP

WLCSP(1)

2019 Microchip Technology Inc.

Datasheet

DS60001513D-page 3

SAM L10/L11 Family

...........continued

Type

Contact/Lead Pitch

Dimensions

0.5 mm

4x4x0.9 mm

VQFN

0.5 mm

5x5x1 mm

TQFP

0.8 mm

7x7x1.2 mm

SSOP

0.65 mm

8.2x5.3x2.0 mm

WLCSP(1)

0.4 mm

2.79x2.79x0.482 mm

Note:

1. Contact local sales for availability.

2019 Microchip Technology Inc.

Datasheet

DS60001513D-page 4

SAM L10/L11 Family

Table of Contents

Features.......................................................................................................................... 1

1. Configuration Summary...........................................................................................15

2. Ordering Information................................................................................................17

3. Block Diagram......................................................................................................... 18

4. Pinouts.....................................................................................................................19

4.1.

4.2.

4.3.

4.4.

4.5.

Multiplexed Signals.................................................................................................................... 20

Oscillators Pinout....................................................................................................................... 22

Serial Wire Debug Interface Pinout............................................................................................ 22

SERCOM Configurations........................................................................................................... 23

General Purpose I/O (GPIO) Clusters........................................................................................24

5. Signal Descriptions List .......................................................................................... 25

6. Power Considerations............................................................................................. 27

6.1.

6.2.

6.3.

6.4.

6.5.

Power Supplies.......................................................................................................................... 27

Power Supply Constraints.......................................................................................................... 27

Power-On Reset and Brown-Out Detectors............................................................................... 28

Voltage Regulators..................................................................................................................... 28

Typical Powering Schematic...................................................................................................... 28

7. Analog Peripherals Considerations......................................................................... 30

7.1.

7.2.

Reference Voltages.................................................................................................................... 31

Analog On Demand Feature...................................................................................................... 31

8. Device Startup......................................................................................................... 33

8.1.

8.2.

8.3.

8.4.

Clocks Startup............................................................................................................................ 33

Initial Instructions Fetching.........................................................................................................33

I/O Pins.......................................................................................................................................33

Performance Level Overview..................................................................................................... 33

9. Product Mapping..................................................................................................... 35

10. Memories.................................................................................................................37

10.1. Embedded Memories................................................................................................................. 37

10.2. NVM Rows................................................................................................................................. 39

10.3. Serial Number............................................................................................................................ 45

11. Processor and Architecture..................................................................................... 46

11.1. Cortex-M23 Processor............................................................................................................... 46

11.2. Nested Vector Interrupt Controller..............................................................................................48

11.3. High-Speed Bus System............................................................................................................ 51

2019 Microchip Technology Inc.

Datasheet

DS60001513D-page 5

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