841N254AKI datasheet, PDF - EEWORLD Datasheet

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841N254AKI: DescriptionClock Generator, 250MHz, CMOS, 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32; CategoryThe embedded processor and controller Microcontrollers and processors; File Size649KB，24 Pages; ManufacturerIDT (Integrated Device Technology)

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841N254AKI Overview

Clock Generator, 250MHz, CMOS, 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32

841N254AKI Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFN
package instruction	5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32
Contacts	32
Reach Compliance Code	not_compliant
ECCN code	EAR99
Other features	IT CAN ALSO OPERATES WITH 3.3V SUPPLY
JESD-30 code	S-XQCC-N32
JESD-609 code	e0
length	5 mm
Humidity sensitivity level	3
Number of terminals	32
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Maximum output clock frequency	250 MHz
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC32,.2SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	240
power supply	2.5/3.3 V
Master clock/crystal nominal frequency	25 MHz
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum slew rate	113 mA
Maximum supply voltage	2.625 V
Minimum supply voltage	2.375 V
Nominal supply voltage	2.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER

841N254AKI Preview

FEMTOCLOCK

Crystal-to-LVDS/HCSL Clock Synthesizer

REFER TO PCN# N1309-01

FOR NEW DESIGNS USE PART NUMBER: ICS841N254BI

ICS841N254I

DATA SHEET

General Description

The ICS841N254I is a 4-output clock synthesizer designed for

S-RIO 1.3 and 2.0 reference clock applications. The device

generates four copies of a selectable 250MHz, 156.25MHz, 125MHz

or 100MHz clock signal with excellent phase jitter performance. The

four outputs are organized in two banks of two LVDS and two HCSL

ouputs.The device uses IDT’s fourth generation FemtoClock® NG

technology for an optimum of high clock frequency and low phase

noise performance, combined with a low power consumption and

high power supply noise rejection. The synthesized clock frequency

and the phase-noise performance are optimized for driving RIO 1.3

and 2.0 SerDes reference clocks. The device supports 3.3V and

2.5V voltage supplies and is packaged in a small 32-lead VFQFN

package. The extended temperature range supports wireless

infrastructure, telecommunication and networking end equipment

requirements.

Features

•

Fourth generation FemtoClock® (NG) technology

Selectable 250MHz, 156.25MHz, 125MHz or 100MHz output

clock synthesized from a 25MHz fundamental mode crystal

Four differential clock outputs (two LVDS and two HCSL outputs)

Crystal interface designed for 25MHz,

parallel resonant crystal

RMS phase jitter @ 156.25MHz, using a 25MHz crystal

(1MHz - 20MHz): 0.27ps (typical)

RMS phase jitter @ 156.25MHz, using a 25MHz crystal

(12kHz - 20MHz): 0.32ps (typical)

Power supply noise rejection PSNR: -50dB (typical)

LVCMOS interface levels for the frequency select input

Full 3.3V or 2.5V supply voltage

Available in both standard (RoHS 5) and Lead-free (RoHS 6)

packages

-40°C to 85°C ambient operating temperature

Function Table

DDOB

nQB0

nQB1

F_SEL0

Inputs

F_SEL1

0 (default)

F_SEL0

0 (default)

Output Frequency with

XTAL

= 25MHz

156.25MHz

32 31 30 29 28 27 26 25

24 IREF

125MHz

100MHz

250MHz

QB0

GND

QB1

Pin Assignment

ICS841N254I

32-lead VFQFN

K Package

5mm x 5mm x 0.925mm

package body

Top View

23 GND

22 nQA0

21 QA0

20 V

DDOA

19 nQA1

18 QA1

17 GND

DDA

nc 4

GND

NOTE: F_SEL[1:0] are asynchronous controls.

REF_CLK

nOEA 7

nOEB

10 11 12 13 14 15 16

BYPASS

REF_SEL

XTAL_OUT

XTAL_IN

F_SEL1

Block Diagram

XTAL_IN

OSC

XTAL_OUT

REF_CLK

REF_SEL

BYPASS

F_SEL[0:1]

nOEA

nOEB

IREF

Pulldown

PFD

LPF

FemtoClock® NG

VCO

625MHz

÷25

÷N

QA0

nQA0

QA1

nQA1

QB0

nQB0

QB1

nQB1

Pulldown

LVDS



LVDS



HCSL



HCSL

ICS841N254AKI REVISION B OCTOBER 21, 2013

ICS841N254I Data Sheet

FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER

Table 1. Pin Descriptions

Number

1, 8, 13, 32

2, 4

5, 17,

23, 25, 31

11,

15,

18, 19

21, 22

26, 27

29, 30

Name

DDA

GND

REF_CLK

nOEA

nOEB

REF_SEL

XTAL_IN,

XTAL_OUT

BYPASS

F_SEL0,

F_SEL1

QA1, nQA1

DDOA

QA0, nQA0

IREF

nQB1, QB1

DDOB

nQB0, QB0

Type

Power

Unused

Power

Input

Output

Power

Output

Input

Output

Power

Output

Description

Core supply pins.

No connect.

Analog power supply.

Power supply ground.

Pulldown Alternative single-ended reference clock input. LVCMOS/LVTTL interface levels.

Pulldown Output enable input. See Table 3D for function. LVCMOS/LVTTL interface levels.

Pulldown Output enable input. See Table 3E for function. LVCMOS/LVTTL interface levels.

Pulldown Reference select input. See Table 3B for function.



LVCMOS/LVTTL interface levels.

Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

Pulldown Bypass mode select pin. See Table 3C for function.



LVCMOS/LVTTL interface levels.

Pulldown Frequency select pin. See Table 3A for function. LVCMOS/LVTTL interface levels.

Differential clock output. LVDS interface levels.

Output supply pin for QAx outputs.

Differential clock output. LVDS interface levels.

External fixed precision resistor (475) from this pin to ground provides a reference

current used for differential current-mode QBx, nQBx clock outputs.

Differential clock output. HCSL interface levels.

Output supply pin for QBx outputs.

Differential clock output. HCSL interface levels.

NOTE:

Pulldown

refers to internal input resistors. See Table 2,

Pin Characteristics,

for typical values.

Table 2. Pin Characteristics

Symbol

PULLDOWN

Parameter

Input Capacitance

Input Pulldown Resistor

Test Conditions

Minimum

Typical

100

Maximum

Units

k

ICS841N254AKI REVISION B OCTOBER 21, 2013

ICS841N254I Data Sheet

FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER

Function Tables

Table 3A. Output Divider and Output Frequency

Inputs

F_SEL1

0 (default)

F_SEL0

0 (default)

Operation

OUT

= f

REF

* 25 ÷ 4

OUT

= f

REF

* 5

OUT

= f

REF

* 4

OUT

= f

REF

* 10

OUT

with f

REF

= 25MHz

156.25MHz

125MHz

100MHz

250MHz

NOTE: F_SEL[1:0] are asynchronous controls.

Table 3B. PLL Reference Clock Select Function Table

Input

REF_SEL

0 (default)

Operation

The crystal interface is selected as reference clock

The REF_CLK input is selected as reference clock

NOTE: REF_SEL is an asynchronous control.

Table 3C. PLL BYPASS Function Table

Input

BYPASS

0 (default)

Operation

PLL is enabled. The reference frequency f

REF

is multiplied by the PLL

feedback divider of 25 and then divided by the selected output divider N.

PLL is bypassed. The reference frequency f

REF

is divided by the selected

output divider N. AC specifications do not apply in PLL bypass mode.

NOTE: BYPASS is an asynchronous control.

Table 3D. nOEA Output Enable Function Table

Input

nOEA

0 (default)

Operation

QA0, nQA0 and QA1, nQA1 outputs are enabled

QA0, nQA0 and QA1, nQA1 outputs are disabled (high-impedance)

NOTE: nOEA is an asynchronous control.

Table 3E. nOEB Output Enable Function Table

Input

nOEB

0 (default)

Operation

QB0, nQB0 and QB1, nQB1 outputs are enabled

QB0, nQB0 and QB1, nQB1 outputs are disabled (high-impedance)

NOTE: nOEB is an asynchronous control.

ICS841N254AKI REVISION B OCTOBER 21, 2013

ICS841N254I Data Sheet

FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the

DC Characteristics or

AC Characteristics

is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Item

Supply Voltage, V

Inputs, V

XTAL_IN

Other Inputs

Outputs, V

(HCSL)

Outputs, I

(LVDS)

Continuous Current

Surge Current

Package Thermal Impedance,



Storage Temperature, T

STG

Rating

3.6V

0V to 2V

-0.5V to V

+ 0.5V

-0.5V to V

+ 0.5V



10mA

15mA

37.7°C/W (0 mps)

-65C to 150C

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics,

= V

DDOA

= V

DDOB

= 3.3V±5% or 2.5V±5%, T

= -40°C to 85°C

Symbol

Parameter

Core Supply Voltage

2.375

Analog Supply Voltage

– 0.30

3.135

DDOA&B

Output Supply Voltage

DDA

DDOA&B

Analog Supply Current

Power Supply Current

Output Supply Current

2.375

2.5

3.3

2.5

3.3

2.5

2.625

3.465

2.625

113

Test Conditions

Minimum

3.135

Typical

3.3

Maximum

3.465

Units

DDA

Table 4B. LVCMOS/LVTTL

Input

DC Characteristics,

= V

DDOA

= V

DDOB

= 3.3V±5% or 2.5V±5%, T

= -40°C to 85°C

Symbol

Parameter

Input High Voltage

Test Conditions

= 3.3V

= 2.5V

Input Low Voltage

nOEA, nOEB,

BYPASS, REF_SEL,

REF_CLK, F_SEL[1:0]

nOEA, nOEB,

BYPASS, REF_SEL,

REF_CLK, F_SEL[1:0]

= 3.3V

= 2.5V

Input High

Current

Input Low

Current

= V

= 2.625V or 3.465V

Minimum

1.7

-0.3

Typical

Maximum

+ 0.3

0.8

0.7

150

Units

µA

= 2.625V or 3.465V,

= 0V

-5

µA

ICS841N254AKI REVISION B OCTOBER 21, 2013

ICS841N254I Data Sheet

FEMTOCLOCK® NG CRYSTAL-TO-LVDS/HCSL CLOCK SYNTHESIZER

Table 4C. LVDS 3.3V DC Characteristics,

= V

DDOA

= 3.3V ± 5% or 2.5V ± 5%, T

= -40°C to 85°C

Symbol

V

Parameter

Differential Output Voltage

Magnitude Change

Offset Voltage

Magnitude Change

1.1

Test Conditions

Minimum

200

Typical

Maximum

550

1.3

Units

Table 5. Crystal Characteristics

Parameter

Mode of Oscillation

Frequency

Equivalent Series Resistance (ESR)

Shunt Capacitance

Test Conditions

Minimum

Typical

Fundamental

MHz



Maximum

Units

ICS841N254AKI REVISION B OCTOBER 21, 2013

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841N254AKI Related Products

	841N254AKI	841N254AKIT
Description	Clock Generator, 250MHz, CMOS, 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32	Clock Generator, 250MHz, CMOS, 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	QFN	QFN
package instruction	5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32	5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32
Contacts	32	32
Reach Compliance Code	not_compliant	not_compliant
ECCN code	EAR99	EAR99
Other features	IT CAN ALSO OPERATES WITH 3.3V SUPPLY	IT CAN ALSO OPERATES WITH 3.3V SUPPLY
JESD-30 code	S-XQCC-N32	S-XQCC-N32
JESD-609 code	e0	e0
length	5 mm	5 mm
Humidity sensitivity level	3	3
Number of terminals	32	32
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Maximum output clock frequency	250 MHz	250 MHz
Package body material	UNSPECIFIED	UNSPECIFIED
encapsulated code	HVQCCN	HVQCCN
Encapsulate equivalent code	LCC32,.2SQ,20	LCC32,.2SQ,20
Package shape	SQUARE	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	240	240
power supply	2.5/3.3 V	2.5/3.3 V
Master clock/crystal nominal frequency	25 MHz	25 MHz
Certification status	Not Qualified	Not Qualified
Maximum seat height	1 mm	1 mm
Maximum slew rate	113 mA	113 mA
Maximum supply voltage	2.625 V	2.625 V
Minimum supply voltage	2.375 V	2.375 V
Nominal supply voltage	2.5 V	2.5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	NO LEAD	NO LEAD
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	20	20
width	5 mm	5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, OTHER	CLOCK GENERATOR, OTHER

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