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70V3379S4BFGI

Description
Dual-Port SRAM, 32KX18, 4.2ns, CMOS, PBGA208, 15 X 15 MM X 1.4 MM, 0.80 MM PITCH, GREEN, FPBGA-208
Categorystorage    storage   
File Size165KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

70V3379S4BFGI Overview

Dual-Port SRAM, 32KX18, 4.2ns, CMOS, PBGA208, 15 X 15 MM X 1.4 MM, 0.80 MM PITCH, GREEN, FPBGA-208

70V3379S4BFGI Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeBGA
package instructionBGA,
Contacts208
Reach Compliance Codecompliant
ECCN code3A991.B.2.B
Maximum access time4.2 ns
Other featuresPIPELINED OUTPUT MODE; SELF TIMED WRITE CYCLE
JESD-30 codeS-PBGA-B208
JESD-609 codee1
length15 mm
memory density589824 bit
Memory IC TypeDUAL-PORT SRAM
memory width18
Humidity sensitivity level3
Number of functions1
Number of terminals208
word count32768 words
character code32000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize32KX18
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN SILVER COPPER
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width15 mm
HIGH-SPEED 3.3V 32K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
IDT70V3379S
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 4.2/5/6ns (max.)
– Industrial: 5ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 128-pin Thin Quad Plastic Flatpack (TQFP)
and 208-pin fine pitch Ball Grid Array, and 256-pin
Ball Grid Array
Green parts available, see ordering information
Functional Block Diagram
UB
L
LB
L
R/W
L
B B
WW
0 1
L L
B B
WW
1 0
R R
UB
R
LB
R
R/W
R
CE
0L
CE
1L
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
R
32K x 18
MEMORY
ARRAY
I/O
0 L
- I/O
1 7 L
CLK
L
Din
_L
Din_R
I/O
0R
- I/O
17R
CLK
R
,.
A
14L
A
0L
CNTRST
L
ADS
L
CNTEN
L
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
14R
A
0R
CNTRST
R
ADS
R
CNTEN
R
4833 tbl 01
JANUARY 2009
1
©2009 Integrated Device Technology, Inc.
DSC 4833/12
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