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IDT74LVC05APG

Description
Inverter, LVC/LCX/Z Series, 6-Func, 1-Input, CMOS, PDSO14, 0.65 MM PITCH, TSSOP-14
Categorylogic    logic   
File Size87KB，5 Pages
ManufacturerIDT (Integrated Device Technology)
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IDT74LVC05APG Overview

Inverter, LVC/LCX/Z Series, 6-Func, 1-Input, CMOS, PDSO14, 0.65 MM PITCH, TSSOP-14

IDT74LVC05APG Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP14,.25
Contacts14
Reach Compliance Codenot_compliant
seriesLVC/LCX/Z
JESD-30 codeR-PDSO-G14
JESD-609 codee0
length5 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeINVERTER
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of functions6
Number of entries1
Number of terminals14
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristicsOPEN-DRAIN
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
power supply3.3 V
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width4.4 mm

IDT74LVC05APG Preview

IDT74LVC05A
3.3V CMOS HEX INVERTER WITH OPEN-DRAIN OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS HEX INVERTER
WITH OPEN-DRAIN OUT-
PUTS, 5 VOLT TOLERANT I/O
FEATURES:
–
–
–
–
–
–
–
–
–
–
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
1.27mm pitch SOIC, 0.65mm pitch SSOP and
0.65mm pitch TSSOP packages
Extended commercial range of – 40°C to +85°C
V
CC
= 3.3V ±0.3V, Normal Range
V
CC
= 2.3V to 3.6V, Extended Range
CMOS power levels (0.4µ W typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
IDT74LVC05A
ADVANCE
INFORMATION
DESCRIPTION:
This hex inverter is built using advanced dual metal CMOS technology.
The outputs of the LVC05A device are open-drain and can be connected
to other open-drain outputs to implement active-low wired-OR or active-
high wired-AND functions. The maximum sink current is 24mA.
The LVC05A has been designed with a +24mA output driver. This driver
is capable of driving a moderate to heavy load while maintaining speed
performance.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V system environ-
ment.
Drive Features for LVC05A:
– High Output Drivers: +24mA
– Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
Functional Block Diagram
PIN CONFIGURATION
A
0
O
0
1
2
3
4
5
6
7
14
13
12
(SO14-1)
11
(SO14-2)
(SO14-3)
V
CC
A
3
O
3
A
4
O
4
A
5
O
5
Ax
Ox
A
1
O
1
A
2
O
2
GND
10
9
8
SOIC/ SSOP/ TSSOP
TOP VIEW
FUNCTION TABLE
(each inverter)
(1)
Inputs
Ax
L
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
Outputs (with pull-up)
Ox
H
L
PIN DESCRIPTION
Pin Names
Ax
Ox
Description
Data Inputs
Data Outputs
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
FEBRUARY 1999
DSC-5164/-
IDT74LVC05A
3.3V CMOS HEX INVERTER WITH OPEN-DRAIN OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through
each V
CC
or GND
LVC QUAD Link
CAPACITANCE
(T
A
= +25°C, f = 1.0MH
Z
)
Unit
V
V
°C
mA
mA
mA
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
LVC QUAD Link
Max.
– 0.5 to +6.5
– 0.5 to +6.5
– 65 to +150
– 50 to +50
– 50
±100
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
5.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
NOTE:
1. As applicable to the device type.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= – 40°c to +85°c
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤5.5V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
—
—
—
—
—
– 0.7
100
—
±50
– 1.2
—
10
µA
V
mV
µA
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
V
O
= 0 to 5.5V
Min.
1.7
2
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
±10
µA
µA
V
Unit
V
Quiescent Power Supply
Current Variation
One input at V
CC
– 0.6V
other inputs at V
CC
or GND
—
—
500
µA
LVC QUAD Link
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
c
1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVC05A
3.3V CMOS HEX INVERTER WITH OPEN-DRAIN OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OL
Parameter
Output LOW Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
Min.
—
—
—
—
—
Max.
0.2
0.4
0.7
0.4
0.55
Unit
V
V
CC
= 2.3V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to +85°C.
OPERATING CHARACTERISTICS, TA = 25°C
V
CC
= 2.5V±0.2V
Symbol
C
PD
Parameter
Power dissipation capacitance per buffer/driver
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
V
CC
= 3.3V±0.3V
Typical
Unit
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V±0.2V
Symbol
Parameter
t
PHL
Propagation Delay
xA to xY
t
SK
(o) Output Skew
(2)
Min.
Max.
Min.
V
CC
= 2.7V
Max.
V
CC
= 3.3V±0.3V
Min.
Max.
Unit
ns
ps
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
3
IDT74LVC05A
3.3V CMOS HEX INVERTER WITH OPEN-DRAIN OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 2.5V ±0.2V
2 x Vcc
Vcc
V
CC
/ 2
150
150
30
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
V
CC
(2)
= 3.3V ±0.3V & 2.7V
6
2.7
1.5
300
300
50
Unit
V
V
V
mV
mV
pF
LVC QUAD Link
SA M E PH AS E
IN PU T TR AN S ITIO N
t
PLH
O U TPU T
t
PLH
O PPO SITE P H AS E
IN PU T TR AN S ITIO N
t
PH L
t
PH L
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
LV C Q U A D L in k
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
G enerator
(1, 2)
V
LOAD
O pen
GND
ENABLE AND DISABLE TIMES
EN ABLE
C O N TR O L
IN PU T
t
PZL
t
PLZ
V
LOAD/2
V
T
t
PH Z
V
T
0V
D ISAB LE
V
IH
V
T
0V
V
LOAD/2
V
LZ
V
OL
V
OH
V
HZ
0V
LV C Q U A D L in k
V
IN
D.U.T.
V
OUT
R
T
500
Ω
C
L
L V C Q U A D L in k
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
O U TPU T
SW ITCH
N O R M ALLY
CLO SED
LO W
t
PZH
O U TPU T
SW ITCH
N O R M ALLY
OP EN
H IGH
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
SET-UP, HOLD, AND RELEASE TIMES
D A TA
IN PU T
TIM IN G
IN PU T
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
L V C Q U A D L in k
GND
Open
LVC QUAD Link
SY N C H RO N O U S
C O N TR O L
t
REM
OUTPUT SKEW - tsk (x)
IN PU T
t
PLH1
t
PH L1
V
IH
V
T
0V
V
OH
AS YN C H RO N O U S
C O N TR O L
t
SU
t
H
PULSE WIDTH
LO W -H IG H -LO W
PU LSE
t
W
H IGH -LO W -H IG H
PU LSE
V
T
LV C Q U A D L in k
O U TP U T 1
t
SK
(x)
t
SK
(x)
V
T
V
OL
V
OH
V
T
O U TP U T 2
t
PLH2
t
PH L2
V
T
V
OL
t
SK
(x)
= t
PL H2
-
t
PLH1
or
t
PH L2
-
t
PHL1
LV C Q U A D L in k
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
4
IDT74LVC05A
3.3V CMOS HEX INVERTER WITH OPEN-DRAIN OUTPUTS
EXTENDED COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
XXX
XX
LVC
IDT
Temp. R ange
Device Type
XX
Package
DC
PY
PG
05A
Sm all Outline IC (SO 14-1)
Shrink Sm all Outline Package (SO14-2)
Thin Shrink Small Outline Package (SO14-3)
Hex Inverter with Open Drain Outputs, +24m A
– 40°C to +85°C
74
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
5
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IDT74LVC05APG Related Products

IDT74LVC05APG IDT74LVC05ADC IDT74LVC05APY
Description Inverter, LVC/LCX/Z Series, 6-Func, 1-Input, CMOS, PDSO14, 0.65 MM PITCH, TSSOP-14 Inverter, LVC/LCX/Z Series, 6-Func, 1-Input, CMOS, PDSO14, 1.27 MM PITCH, SOIC-14 Inverter, LVC/LCX/Z Series, 6-Func, 1-Input, CMOS, PDSO14, 0.65 MM PITCH, SSOP-14
Is it Rohs certified? incompatible incompatible incompatible
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP SOIC SSOP
package instruction TSSOP, TSSOP14,.25 SOP, SOP14,.25 SSOP, SSOP14,.3
Contacts 14 14 14
Reach Compliance Code not_compliant not_compliant _compli
series LVC/LCX/Z LVC/LCX/Z LVC/LCX/Z
JESD-30 code R-PDSO-G14 R-PDSO-G14 R-PDSO-G14
JESD-609 code e0 e0 e0
length 5 mm 8.65 mm 6.2 mm
Load capacitance (CL) 50 pF 50 pF 50 pF
Logic integrated circuit type INVERTER INVERTER INVERTER
MaximumI(ol) 0.024 A 0.024 A 0.024 A
Number of functions 6 6 6
Number of entries 1 1 1
Number of terminals 14 14 14
Maximum operating temperature 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Output characteristics OPEN-DRAIN OPEN-DRAIN OPEN-DRAIN
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP SOP SSOP
Encapsulate equivalent code TSSOP14,.25 SOP14,.25 SSOP14,.3
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE, SHRINK PITCH
power supply 3.3 V 3.3 V 3.3 V
Certification status Not Qualified Not Qualified Not Qualified
Schmitt trigger NO NO NO
Maximum seat height 1.2 mm 1.75 mm 2 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 2.3 V 2.3 V 2.3 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn85Pb15) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 1.27 mm 0.65 mm
Terminal location DUAL DUAL DUAL
width 4.4 mm 3.9 mm 5.3 mm

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