3.3V Dual LVTTL/LVCMOS-to-Differential
LVPECL Translator
The MC100ES60T22 is a low skew dual LVTTL/LVCMOS to differential LVPECL
translator. The low voltage PECL levels, small package, and dual gate design are ideal for
clock translation applications.
Features
•
•
•
•
•
•
280 ps typical propagation delay
100 ps max output-to-output skew
LVPECL operating range: V
CC
= 3.135 V to 3.8 V
8-lead SOIC and 8-lead TSSOP packages
Ambient temperature range –40°C to +85°C
8-lead SOIC Pb-free package available
MC100ES60T22
DATA SHEET
D SUFFIX
8-LEAD SOIC PACKAGE
CASE 751-07
EF SUFFIX
8-LEAD SOIC PACKAGE
Pb-FREE PACKAGE
CASE 751-07
Q0
1
8
V
CC
DT SUFFIX
8-LEAD TSSOP PACKAGE
CASE 1640-01
EJ SUFFIX
8-LEAD SOIC PACKAGE
Pb-FREE PACKAGE
CASE 1640-01
Q0
2
LVPECL
LVTTL/LVCMOS
7
D0
Q1
3
6
D1
ORDERING INFORMATION
Device
MC100ES60T22D
MC100ES60T22DR2
Package
SOIC-8
SOIC-8
SOIC-8 (Pb-Free)
SOIC-8 (Pb-Free)
TSSOP-8
TSSOP-8
TSSOP-8 (Pb-Free)
TSSOP-8 (Pb-Free)
Q1
4
5
GND
MC100ES60T22EF
MC100ES60T22EFR2
MC100ES60T22DT
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
MC100ES60T22DTR2
MC100ES60T22EJ
MC100ES60T22EJR2
PIN DESCRIPTION
Pin
D0, D1
Qn, Qn
V
CC
GND
Function
LVTTL/LVCMOS Inputs
LVPECL Differential Outputs
Positive Supply
Negative Supply
MPC100ES60T22 REVISION 4 AUGUST 14, 2009
1
©2009 Integrated Device Technology, Inc.
MPC100ES60T22 Data Sheet
Table 1. General Specifications
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
θ
JA
Thermal Resistance (Junction-to-Ambient)
Human Body Model
Machine Model
0 LFPM, 8 SOIC
500 LFPM, 8 SOIC
0 LFPM, 8 TSSOP
500 LFPM, 8 TSSOP
3.3V DUAL LVTTL/LVCMOS-TO-DIFFERENTIAL LVPECL TRANSLATOR
Value
75 kΩ
75 kΩ
> 2000 V
> 200 V
190°C/W
130°C/W
185°C/W
140°C/W
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Table 2. Absolute Maximum Ratings
(1)
Symbol
V
SUPPLY
V
IN
I
out
T
A
T
STG
Rating
Power Supply Voltage
Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Conditions
Difference between V
CC
& V
EE
V
CC
– V
EE
≤
3.6 V
Continuous
Surge
Rating
3.9
V
CC
+ 0.3
V
EE
– 0.3
50
100
–40 to +85
–65 to +150
Units
V
V
V
mA
mA
°C
°C
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 3. DC Characteristics
(V
CC
= 3.135 V to 3.8 V; V
EE
= 0 V)
-40°C
Symbol
V
OH(1)
V
OL(1)
Characteristic
Output HIGH Voltage
Output LOW Voltage
Min
V
CC
– 1150
V
CC
– 1950
Typ
V
CC
– 1020
V
CC
– 1620
Max
V
CC
– 800
V
CC
– 1250
Min
V
CC
– 1200
V
CC
– 2000
0°C to 85°C
Typ
V
CC
– 970
V
CC
– 1680
Max
V
CC
– 750
V
CC
– 1300
Unit
mV
mV
1. Outputs are terminated through a 50
Ω
resistor to V
CC
– 2 volts.
Table 4. LVTTL / LVCMOS Input DC Characteristics
(V
CC
= 3.135 V to 3.8 V)
-40°C
Symbol
I
IN
V
IK
V
IH
V
IL
Characteristic
Input Current
Input Clamp Voltage
Input HIGH Voltage
Input LOW Voltage
Condition
V
IN
= V
CC
I
IN
= –18 mA
2.0
Min
Typ
Max
±150
–1.2
V
CC
+0.3
0.8
2.0
Min
0°C to 85°C
Typ
Max
±150
–1.2
V
CC
+0.3
0.8
Unit
µA
V
V
V
MPC100ES60T22 REVISION 4 AUGUST 14, 2009
2
©2009 Integrated Device Technology, Inc.
MPC100ES60T22 Data Sheet
3.3V DUAL LVTTL/LVCMOS-TO-DIFFERENTIAL LVPECL TRANSLATOR
Table 5. AC Characteristics
(V
CC
= 3.134 V to 3.8 V; V
EE
= 0 V)
-40°C
Symbol
f
max
t
PLH,
t
PHL
t
SKEW
Characteristic
Maximum Toggle Frequency
Propagation Delay
Skew
part-to-part
RMS (1σ)
350
50
750
400
100
260
Min
Typ
Max
1
400
300
1
350
50
750
400
100
280
Min
25°C
Typ
Max
1
400
300
1
350
50
750
400
100
280
Min
85°C
Typ
Max
1
450
350
1
Unit
GHz
ps
ps
ps
mV
ps
t
JITTER
Cycle-to-Cycle Jitter
V
outPP
Output Peak-to-Peak Voltage
t
r
/ t
f
Output Rise/Fall Times (20% – 80%)
Q
Driver
Device
Qb
50Ω
50Ω
D
Receiver
Device
Db
V TT
Figure 2. Typical Termination for Output Driver and Device Evaluation
MPC100ES60T22 REVISION 4 AUGUST 14, 2009
3
©2009 Integrated Device Technology, Inc.
MPC100ES60T22 Data Sheet
3.3V DUAL LVTTL/LVCMOS-TO-DIFFERENTIAL LVPECL TRANSLATOR
PACKAGE DIMENSIONS
PAGE 1 OF 2
CASE 751-07
ISSUE U
8-LEAD SOIC PACKAGE
MPC100ES60T22 REVISION 4 AUGUST 14, 2009
4
©2009 Integrated Device Technology, Inc.
MPC100ES60T22 Data Sheet
3.3V DUAL LVTTL/LVCMOS-TO-DIFFERENTIAL LVPECL TRANSLATOR
PACKAGE DIMENSIONS
PAGE 2 OF 2
CASE 751-07
ISSUE U
8-LEAD SOIC PACKAGE
MPC100ES60T22 REVISION 4 AUGUST 14, 2009
5
©2009 Integrated Device Technology, Inc.
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