1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[2]
.... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[2]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[2]
.................................–0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
4.5V–5.5V
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max.
,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
Com’l
CE > V
CC
– 0.3V,
Com’l
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0 Ind’l
Ind’l
Note:
2. Minimum voltage is–2.0V for pulse durations of less than 20 ns.
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
7C1049B-12
Min.
2.4
0.4
2.2
–0.3
–1
–1
V
CC
+0.3
0.8
+1
+1
240
40
Max.
7C1049B-15
Min.
2.4
0.4
2.2
–0.3
–1
–1
V
CC
+0.3
0.8
+1
+1
220
40
Max.
7C1049B-17
Min.
2.4
0.4
2.2
–0.3
–1
–1
V
CC
+0.3
0.3
+1
+1
195
40
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB2
8
L
L
-
-
-
8
-
-
-
8
0.5
8
0.5
mA
mA
mA
mA
Document #: 001-06501 Rev. **
Page 2 of 10
[+] Feedback
CY7C1049BN
Electrical Characteristics
Over the Operating Range (continued)
Test Conditions
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[2]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max.
,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Com’l
Com’l
Ind’l
Ind’l
L
L
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.3
–1
–1
7C1049B-20
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
185
40
2.2
–0.3
–1
–1
Max.
7C1049B-25
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
180
40
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB2
8
0.5
8
0.5
8
0.5
8
0.5
mA
mA
mA
mA
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255Ω
R1 481Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255Ω
GND
≤
3 ns
R1 481Ω
ALL INPUT PULSES
3.0V
90%
10%
90%
10%
≤
3 ns
Equivalent to:
THÉVENIN EQUIVALENT
167Ω
1.73V
OUTPUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06501 Rev. **
Page 3 of 10
[+] Feedback
CY7C1049BN
Switching Characteristics
[4]
Over the Operating Range
7C1049B-12
Parameter
Read Cycle
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
V
CC
(typical) to the First Access
[5]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[7]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[7]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[7]
WE LOW to High Z
[6, 7]
12
10
10
0
0
10
7
0
3
6
0
12
15
12
12
0
0
12
8
0
3
7
3
6
0
15
17
12
12
0
0
12
8
0
3
8
0
6
3
7
0
17
3
12
6
0
7
3
7
1
12
12
3
15
7
0
7
1
15
15
3
17
8
1
17
17
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C1049B-15
Min.
Max.
7C1049B-17
Min.
Max.
Unit
Write Cycle
[8, 9]
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. t
power
time has to be provided initially before a read/write operation is
started.
6. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of
either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
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