Data Sheet
PC8548E
PowerQUICC III Integrated Processor
Datasheet DS0831
FEATURES
•
Embedded e500 Core, Initial Offerings up to 1.2 GHz
– Dual Dispatch Superscalar, 7‐stage Pipeline Design with
out‐of‐order Issue and Execution
– 3065 MIPS at 1333 MHz (Estimated Dhrystone 2.1)
•
36‐bit Physical Addressing
•
Enhanced Hardware and Software Debug Support
•
Double‐precision Embedded Scalar and Vector Floating‐point
APUs
•
Memory Management Unit (MMU)
•
Integrated L1/L2 Cache
– L1 Cache‐32 KB Data and 32 KB Instruction Cache with
Line‐locking Support
– L2 Cache‐512 KB (8‐Way Set Associative); 512 KB/256
KB/128 KB/64 KB Can Be Used As SRAM
– L1 and L2 Hardware Coherency
– L2 Configurable As SRAM, Cache and I/O Transactions
Can Be Stashed Into L2 Cache Regions
•
Integrated DDR Memory Controller With Full ECC Support,
Supporting:
– 200 MHz Clock Rate (400 MHz Data Rate), 64‐bit,
2.5V/2.6V I/O, DDR SDRAM
•
Integrated Security Engine Supporting DES, 3DES, MD‐5, SHA‐
1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC‐4 Encryption
Algorithms
•
Four On‐chip Triple‐speed Ethernet Controllers (GMACs)
Supporting 10‐ and 100‐Mbps, and 1‐Gbps
Ethernet/IEEE*802.3 Networks with MII, RMII, GMII, RGMII,
RTBI and TBI Physical Interfaces
– TCP/IP Checksum Acceleration
– Advanced QoS Features
•
General‐purpose I/O (GPIO)
•
Serial RapidIO and PCI Express High‐speed Interconnect
Interfaces, Supporting
– Single x8 PCI Express, or Single x4 PCI Express and
Single 4x Serial RapidIO
•
On‐chip Network (OCeaN) Switch Fabric
•
Multiple PCI Interface Support
– 64‐bit PCI 2.2 Bus Controller (Up to 66 MHz, 3.3V I/O)
– 64‐bit PCI‐X Bus Controller (Up to 133 MHz, 3.3V I/O),
or Flexibility to Configure Two 32‐bit PCI Controllers
•
166 MHz, 32‐bit, 3.3V I/O, Local Bus with Memory
Controller
•
Integrated Four‐channel DMA Controller
•
Dual I2C and Dual Universal Asynchronous
Receiver/Transmitter (DUAR) Support
•
Programmable Interrupt Controller (PIC), IEEE 1149.1 JTAG
Test Access Port
•
1.1V Core Voltage with 3.3V and 2.5V I/O, 783‐pin HITCE
and PBGA Packages
DESCRIPTION
The PC8548E contains a Power Architecture
™
processor
core. The PC8548E integrates a processor that implements
the Power Architecture with system logic required for net‐
working, storage, and general‐purpose embedded
applications. For functional characteristics of the processor,
refer to the PC8548E Integrated Processor Preliminary Ref‐
erence Manual.
SCREENING
•
Full Military Temperature Range (T
C
= –55C, T
J
= +125C)
•
Industrial Temperature Range (T
C
= –40C, T
J
= +110C)
Whilst e2v technologies has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any
use thereof and also reserves the right to change the specification of goods without notice. e2v technologies accepts no liability beyond the set out in its
standard conditions of sale in respect of infringement of third party patents arising from the use of devices in accordance with information contained
herein.
e2v technologies (uk) limited, Waterhouse Lane, Chelmsford, Essex CM1 2QU United Kingdom Holding Company: e2v technologies plc
Telephone: +44 (0)1245 493493 Facsimile: +44 (0)1245 492492
Contact e2v by e‐mail: enquiries@e2v.com or visit www.e2v.com for global sales and operations centres.
© e2v technologies (uk) limited 2016
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PC8548E
1.
PC8548E ARCHITECTURE GENERAL OVERVIEW
Figure 1‐1.
DDR
SDRAM
Flash
SDRAM
GPIO
PC8548E Block Diagram
DDR/DDR2/
Memory Controller
Security
Engine
512-Kbyte
L2 Cache/
SRAM
e500 Core
e500
Coherency
Module
32-Kbyte L1
Instruction
Cache
32-Kbyte
L1 Data
Cache
Local Bus Controller
Programmable Interrupt
Controller (PIC)
DUART
I
2
C
Controller
I
2
C
Controller
eTSEC
10/100/1Gb
eTSEC
10/100/1Gb
eTSEC
10/100/1Gb
eTSEC
10/100/1Gb
XOR
Engine
IRQs
Serial
Core Complex
Bus
I
2
C
I
2
C
MII, GMII, TBI,
RTBI, RGMII,
RMII
MII, GMII, TBI,
RTBI, RGMII,
RMII
MII, GMII, TBI,
RTBI, RGMII,
RMII
RTBI, RGMII,
RMII
Serial RapidIO
TM
or
PCI Express
OceaN
Switch
Fabric
32-bit PCI Bus Interface
(If 64-bit not used)
32-bit PCI/
64-bit PCI/PCI-X
Bus Interface
4-Channel DMA
Controller
4x RapidlO
x8 PCI Express
PCI 32-bit
66 MHz
PCI/PCI-X
133 MHz
1.1
Features Overview
The following list provides an overview of the PC8548E feature set:
• High‐performance 32‐bit Book E–enhanced core that implements the Power Architecture
– 32‐Kbyte L1 instruction cache and 32‐Kbyte L1 data cache with parity protection. Caches
can be locked entirely or on a per‐line basis, with separate locking for instructions and data
– Signal‐processing engine (SPE) APU (auxiliary processing unit). Provides an extensive
instruction set for vector (64‐bit) integer and fractional operations. These instructions use
both the upper and lower words of the 64‐bit GPRs as they are defined by the SPE APU
– Double‐precision floating‐point APU. Provides an instruction set for double‐precision (64‐
bit) floating‐point instructions that use the 64‐bit GPRs
– 36‐bit real addressing
– Embedded vector and scalar single‐precision floating‐point APUs. Provide an instruction set
for single‐precision (32‐bit) floating‐point instructions
– Memory management unit (MMU). Especially designed for embedded applications.
Supports 4‐Kbyte–4‐Gbyte page sizes
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PC8548E
– Enhanced hardware and software debug support
– Performance monitor facility that is similar to, but separate from, the PC8548E performance
monitor
The e500 defines features that are not implemented on this device. It also generally defines some features
that this device implements more specifically. An understanding of these differences can be critical to ensure
proper operations.
• 512‐Kbyte L2 cache/SRAM
– Flexible configuration
– Full ECC support on 64‐bit boundary in both cache and SRAM modes
– Cache mode supports instruction caching, data caching, or both
– External masters can force data to be allocated into the cache through programmed
memory ranges or special transaction types (stashing)
– 1, 2, or 4 ways can be configured for stashing only
– Eight‐way set‐associative cache organization (32‐byte cache lines)
– Supports locking entire cache or selected lines. Individual line locks are set and cleared
through Book E instructions or by externally mastered transactions
– Global locking and flash clearing done through writes to L2 configuration registers
– Instruction and data locks can be flash cleared separately
– SRAM features include the following:
– I/O devices access SRAM regions by marking transactions as snoopable (global)
– Regions can reside at any aligned location in the memory map
– Byte‐accessible ECC is protected using read‐modify‐write transaction accesses for smaller‐
than‐cache‐line accesses
• Address translation and mapping unit (ATMU)
– Eight local access windows define mapping within local 36‐bit address space
– Inbound and outbound ATMUs map to larger external address spaces
– Three inbound windows plus a configuration window on PCI/PCI‐X and PCI Express
– Four inbound windows plus a default window on RapidIO
– Four outbound windows plus default translation for PCI/PCI‐X and PCI Express
– Eight outbound windows plus default translation for RapidIO with segmentation and sub‐
segmentation support
• DDR/DDR2 memory controller
– Programmable timing supporting DDR and DDR2 SDRAM
– 64‐bit data interface
– Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes
– DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports
– Full ECC support
– Page mode support
– Up to 16 simultaneous open pages for DDR
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PC8548E
– Up to 32 simultaneous open pages for DDR2
– Contiguous or discontiguous memory mapping
– Read‐modify‐write support for RapidIO atomic increment, decrement, set, and clear
transactions
– Sleep mode support for self‐refresh SDRAM
– On‐die termination support when using DDR2
– Supports auto refreshing
– On‐the‐fly power management using CKE signal
– Registered DIMM support
– Fast memory access via JTAG port
– 2.5V SSTL_2 compatible I/O (1.8V SSTL_1.8 for DDR2)
– Support for battery‐backed main memory
• Programmable interrupt controller (PIC)
– Programming model is compliant with the OpenPIC architecture
– Supports 16 programmable interrupt and processor task priority levels
– Supports 12 discrete external interrupts
– Supports 4 message interrupts with 32‐bit messages
– Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
– Four global high resolution timers/counters that can generate interrupts
– Supports a variety of other internal interrupt sources
– Supports fully nested interrupt delivery
– Interrupts can be routed to external pin for external processing
– Interrupts can be routed to the e500 core’s standard or critical interrupt inputs
– Interrupt summary registers allow fast identification of interrupt source
• Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec, IKE,
WTLS/WAP, SSL/TLS, and 3GPP
– Four crypto‐channels, each supporting multi‐command descriptor chains
– Dynamic assignment of crypto‐execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
– PKEU: public key execution unit
– RSA and Diffie‐Hellman; programmable field size up to 2048 bits
– Elliptic curve cryptography with F
2
m and F(p) modes and programmable field size up to 511 bits
– DEU: Data Encryption Standard execution unit
– DES, 3DES
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
– AESU: Advanced Encryption Standard unit
– Implements the Rijndael symmetric key cipher
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PC8548E
– ECB, CBC, CTR, and CCM modes
– 128‐, 192‐, and 256‐bit key lengths
– AFEU: ARC four execution unit
– Implements a stream cipher compatible with the RC4 algorithm
– 40‐ to 128‐bit programmable key
– MDEU: message digest execution unit
– SHA with 160‐ or 256‐bit message digest
– MD5 with 128‐bit message digest
– HMAC with either algorithm
– KEU: Kasumi execution unit
– Implements F8 algorithm for encryption and F9 algorithm for integrity checking
– Also supports A5/3 and GEA‐3 algorithms
– RNG: random number generator
– XOR engine for parity checking in RAID storage applications
• Dual I
2
C controllers
– Two‐wire interface
– Multiple master support
– Master or slave I
2
C mode support
– On‐chip digital filtering rejects spikes on the bus
• Boot sequencer
– Optionally loads configuration data from serial ROM at reset via the I
2
C interface
– Can be used to initialize configuration registers and/or memory
– Supports extended I
2
C addressing mode
– Data integrity checked with preamble signature and CRC
• DUART
– Two 4‐wire interfaces (SIN, SOUT, RTS, CTS)
– Programming model compatible with the original 16450 UART and the PC16550D
• Local bus controller (LBC)
– Multiplexed 32‐bit address and data bus operating at up to 133 MHz
– Eight chip selects support eight external slaves
– Up to eight‐beat burst transfers
– The 32‐, 16‐, and 8‐bit port sizes are controlled by an on‐chip memory controller
– Three protocol engines available on a per chip select basis:
– General‐purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
– Parity support
– Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)
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