M368L6423BT0
184pin Unbuffered DDR SDRAM MODULE
512MB DDR SDRAM MODULE
(64Mx64(32Mx64*2 bank) based on 32Mx8 DDR SDRAM)
Unbuffered 184pin DIMM
64-bit Non-ECC/Parity
Revision 0.5
April. 2000
- -1 -
Rev. 0.5 April. 2000
M368L6423BT0
Revision History
Revision 0 (Aug 1998)
1. First release for internal usage
184pin Unbuffered DDR SDRAM MODULE
Revision 0.1 (Aug. 1999)
1. Modified binning policy
From
To
-Z (133Mhz)
-Z (133Mhz/266Mbps@CL=2)
-8 (125Mhz)
-Y (133Mhz/266Mbps@CL=2.5)
-0 (100Mhz)
-0 (100Mhz/200Mbps@CL=2)
2.Modified the following AC spec values
From.
-Z
tAC
tDQSCK
tDQSQ
tDS/tDH
tCDLR
*1
tPRE
*1
tRPST
*1
tHZQ
*1
*1
To.
-0
+/- 1ns
+/- 1ns
+/- 0.75ns
0.75 ns
-Z
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
-Y
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
-0
+/- 0.8ns
+/- 0.8ns
+/- 0.6ns
0.6 ns
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/-0.8ns
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
2.5tCK-tDQSS
1tCK +/- 0.75ns
tCK/2 +/- 0.75ns
tCK/2 +/- 0.75ns
2.5tCK-tDQSS
1tCK +/- 1ns
tCK/2 +/- 1ns
tCK/2 +/- 1ns
: Changed description method for the same functionality. This means no difference from the previous version.
3.Changed the following AC parameter symbol From tDQCK To tAC
Output data access time from CK/CK
Revision 0.2 (Sept. 1999)
1. Changed the odering information.
1-1. Exclude KM mark.
From
KMM368...
1-2. PCB Revison
From
- Blank: 1st generation
-A
: 2nd generation
-B
: 2nd generation
Example:KMM368L6423AT
1-3. Modified binning policy
From
- 0 (100Mhz/200Mbps@CL=2)
- Z (133Mhz/266Mbps@CL=2)
- Y (133Mhz/266Mbps@CL=2.5)
To
M368.....
To
- 0: 1st gernation
- 1: 2nd generation
- 2: 3nd generation
M368L6423AT0
To
- A0 (100Mhz/200Mbps@CL=2)
- A2 (133Mhz/266Mbps@CL=2)
- B0 (133Mhz/266Mbps@CL=2.5)
-0-
Rev. 0.5 April. 2000
M368L6423BT0
Revision 0.3 (December. 1999)
1. Changed from 3.3V to 2.5V in VDDSPD power.
184pin Unbuffered DDR SDRAM MODULE
Revision 0.4 (April. 2000)
< Page 3 >
1. Changed from 1450mil to 1250mil in PCB height.
2. Changed pin 90 from WP to NC in pin configuration table.
3. Changed in pin configuration table as followings.
pin 16 : CK0 -> CK1
pin 17 : CK0 -> /CK1
pin 137 : CK1 -> CK0
pin 138 : CK1 -> /CK0
4. Removed WP in pin description.
< Page 4>
5. Changed Clock wiring as followings.
CK0 / CK0 6SDRAMs -> 4SDRAMs
CK1 / CK1 4SDRAMs -> 6SDRAMs
6. Changed bypassing to reflect common Vdd/Vddq plane.
7. Added A13, BA1.
8. Removed WP from serial PD.
< Page 5>
9.
Changed Power & DC operating condition.
Parameter
I/O Reference voltage
Input logic high voltage
Input logic low voltage
Input leakage current
Output High Current (V
OUT
= 1.95V)
Output Low Current (V
OUT
= 0.35V)
Symbol
Min
V
REF
V
IH
(DC)
V
IL
(DC)
I
I
I
OH
I
OL
1.15
From
Max
1.35
V
DDQ
+0.3
V
REF
-0.18
5
To
Min
0.49*VDDQ
V
REF
+0.15
-0.3
-2
-16.8
16.8
Max
0.51*VDDQ
V
DDQ
+0.3
V
REF
-0.15
2
V
REF
+0.18
-0.3
-5
-15.2
15.2
< Page 6 >
10. Added Overshoot/Undershoot spec
. Vih(max) = 4.2V, the overshoot voltage duration is
≤
3ns at VDD.
. Vil(min) =- 1.5V, the overshoot voltage duration is
≤
3ns at VSS.
< Page 6,7 >
11.Changed AC operating conditions as follows.
Parameter/Condition
Symbol
Min
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC)
Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC)
Input Differential Voltage, CK and CK inputs
VID(AC)
0.7
VREF + 0.35
VREF - 0.35
VDDQ+0.6
0.62
From
Max
Min
VREF + 0.31
VREF - 0.31
VDDQ+0.6
To
Max
-1-
Rev. 0.5 April. 2000
M368L6423BT0
< Page 7 >
12. Changed Input/Output capacitance as follows.
Parameter
Input capacitance(A
0
~ A
12
, BA
0
~ BA
1
,RAS,CAS,
WE )
Input capacitance(CKE
0,
CKE
1
)
Input capacitance( CS
0
,CS
1
)
Input capacitance( CLK
0
, CLK
1,
CLK
2
)
Data & DQS input/output capacitance(DQ
0
~DQ
63
)
Input capacitance(DM
0
~DM
8
)
184pin Unbuffered DDR SDRAM MODULE
Symbol
Min
C
IN1
C
IN2
C
IN3
C
IN4
C
OUT
C
IN5
-
-
-
-
-
-
From
Max
90
62
55
38
16
16
Min
65
42
42
27
10
10
To
Max
81
50
50
34
13
13
< page 8, 9>
13. Changed AC parameters as follows.
Parameter
tDQSQ
tDV
from
+/- 0.5(PC266), +/- 0.6(PC200)
+/- 0.35tCK
to
+0.5(PC266), +0.6(PC200)
-
Removed
Comments
14. Added AC parameters as follows
Parameter
Symbol
-A2(PC266@CL=2)
Min
Output DQS valid window
Clock half period
QFC setup to first DQS edge on reads
QFC hold after last DQS edge on reads
Write command to QFC delay on write
Write burst end to QFC delay on write
Write burst end to QFC delay on write inter-
rupted
by Precharge
tQH
tHP
tQCS
tDQCH
tQCSW
tQCHW
tQCHWI
1.25ns
1.25ns
tHPmin
-0.75ns
tCLmin
or tCH-
0.9
0.4
Max
-
-
-B0(PC266@CL=2.5)
Min
tHPmin
-0.75ns
tCLmin
or tCHmin
0.9
0.4
Max
-
-
-A0(PC200@CL=2)
Min
tHPmin
-1.0ns
tCLmin
or tCHmin
0.9
0.4
Max
-
-
1.1
0.6
4.0
0.5tCK
1.5tCK
1.1
0.6
4.0
1.1
0.6
4.0
1.25ns
1.25ns
0.5tCK
1.5tCK
1.25ns
1.25ns
0.5tCK
1.5tCK
< Page 12>
15.Changed from 1450mil to 1250mil in Package dimension.
Revision 0.5 (April. 2000)
1. Changed from A-die to B-die.
-2-
Rev. 0.5 April. 2000
M368L6423BT0
184pin Unbuffered DDR SDRAM MODULE
M368L6423BT0 DDR SDRAM 184pin DIMM
64Mx64 DDR SDRAM 184pin DIMM based on 32Mx8
GENERAL DESCRIPTION
The Samsung M368L6423BT0 is 32M bit x 64 Double Data
Rate SDRAM high density memory module based on first gen.
of 256Mb DDR SDRAM respectively. The Samsung M368-
L6423BT0 consists of sixteen CMOS 32M x 8 bit with 4banks
Double Data Rate SDRAMs in 66pin TSOP-II(400mil) pack-
ages mounted on a 184pin glass-epoxy substrate. Four 0.1uF
decoupling capacitors are mounted on the printed circuit board
in parallel for each DDR SDRAM. The M368L6423BT0 Dual In-
line Memory Module and is intended for mounting into 184pin
edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies and burst lengths allows the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
FEATURE
• Performance range
Part No.
M368L6423BT0-C(L)A2
M368L6423BT0-C(L)B0
M368L6423BT0-C(L)A0
Max Freq.
133MHz(7.5ns@CL=2)
133MHz(7.5ns@CL=2.5)
100MHz(10ns@CL=2)
SSTL_2
Interface
• Power supply
Vdd: 2.5V
±
0.2V
Power: C - normal, L - Low power
• MRS cycle with address key programs
CAS Latency (Access from column address):2,2.5
Burst length ;2, 4, 8
Data scramble ;Sequential & Interleave
• Serial presence detect with EEPROM
• PCB :
Height 1250 (mil),
double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front
1 VREF
2
DQ0
3
VSS
4
DQ1
5 DQS0
6
DQ2
7
VDD
8
DQ3
9
NC
10
NC
11 VSS
12 DQ8
13 DQ9
14 DQS1
15 VDDQ
16 CK1
17 /CK1
18 VSS
19 DQ10
20 DQ11
21 CKE0
22 VDDQ
23 DQ16
24 DQ17
25 DQS2
26 VSS
27
A9
28 DQ18
29
A7
30 VDDQ
31 DQ19
Pin Front Pin
32
A5
62
33 DQ24 63
34 VSS 64
35 DQ25 65
36 DQS3 66
37
A4
67
38 VDD 68
39 DQ26 69
40 DQ27 70
41
A2
71
42 VSS 72
43
A1
73
44 *CB0 74
45 *CB1 75
46 VDD 76
47 *DQS8 77
48
A0
78
49 *CB2 79
50 VSS 80
51 *CB3 81
52
BA1 82
KEY
83
53 DQ32 84
54 VDDQ 85
55 DQ33 86
56 DQS4 87
57 DQ34 88
58 VSS 89
59
BA0 90
60 DQ35 91
61 DQ40 92
Front
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
/CK2
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
*A13
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
Back
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
*CB4
*CB5
VDDQ
CK0
/CK0
VSS
*DM8
A10
*CB6
VDDQ
*CB7
KEY
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
/RAS
DQ45
VDDQ
CS0
CS1
DM5
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
PIN DESCRIPTION
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CKE0,CKE1
CS0, CS1
RAS
CAS
WE
DM0 ~ 7
VDD
VDDQ
VSS
VREF
VDDSPD
SDA
SCL
SA0 ~ 2
VDDID
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
Data Strobe input/output
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
Data - in mask
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
Power supply for reference
Serial EEPROM Power
Supply (2.5V)
Serial data I/O
Serial clock
Address in EEPROM
VDD identification flag
CK0,CK0 ~ CK2, CK2 Clock input
NC
No connection
* These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
-3-
Rev. 0.5 April. 2000