PSD502B1-15L datasheet, PDF - EEWORLD Datasheet

PSD502B1-15L: DescriptionMultifunction Peripheral, CMOS, CQCC68,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，130 Pages; ManufacturerWaferscale Integration Inc.

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PSD502B1-15L Overview

Multifunction Peripheral, CMOS, CQCC68,

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Waferscale Integration Inc.
package instruction	QCCJ, LDCC68,1.0SQ
Reach Compliance Code	unknown
Maximum access time	1.5e-7 ns
Other features	32K X 16 REPROGRAMMABLE EPROM; GENERAL PURPOSE ZPLD, DECODING ZPLD & PERIPHERAL ZPLD
Address bus width	16
boundary scan	NO
Bus compatibility	8031; 80196; 80196SP; 80186; 68HC11; 68HC16; 68330; 68331; 68340; 68302; 16000; Z80; Z8
maximum clock frequency	34.48 MHz
External data bus width	16
JESD-30 code	S-CQCC-J68
JESD-609 code	e0
Number of I/O lines	40
Number of serial I/Os
Number of terminals	68
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
RAM (number of words)	512
ROM size (bits)	512 Bits
Maximum standby current	0.00002 A
Maximum slew rate	45 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
UV erasable	Y

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