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Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> PCX7410VGSU500NE
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PCX7410VGSU500NE

Description
RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size809KB，46 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
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PCX7410VGSU500NE Overview

RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360

PCX7410VGSU500NE Parametric

Parameter NameAttribute value
MakerMicrochip
package instructionCOLUMN INTERPOSER, CERAMIC, CGA-360
Reach Compliance Codeunknown
ECCN code3A001.A.3
Address bus width32
bit size32
boundary scanYES
maximum clock frequency133 MHz
External data bus width64
FormatFLOATING POINT
Integrated cacheYES
JESD-30 codeS-CBGA-X360
length25 mm
low power modeYES
Number of terminals360
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeCGA
Package shapeSQUARE
Package formGRID ARRAY
Certification statusNot Qualified
Maximum seat height4.2 mm
speed500 MHz
Maximum supply voltage1.55 V
Minimum supply voltage1.45 V
Nominal supply voltage1.5 V
surface mountYES
technologyCMOS
Terminal formUNSPECIFIED
Terminal pitch1.27 mm
Terminal locationBOTTOM
width25 mm
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR, RISC

PCX7410VGSU500NE Preview

Features
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22.8 SPECint95 (estimated), 17SPECfp95 at 500 MHz (estimated)
917MIPS at 500 MHz
Selectable Bus Clock (14 CPU Bus Dividers Up To 9x)
Seven Selectable Core-to-L2 Frequency Divisors
Selectable 603 Interface Voltage Below 3.3V (1.8V, 2.5V)
Selectable L2 interface of 1.8V or 2.5V
P
D
Typical 5.3W at 500 MHz, Full Operating Conditions
Nap, Doze and Sleep Modes for Power Saving
Superscalar (Four Instructions fetched per Clock Cycle)
4 GB Direct Addressing Range
Virtual Memory: 4 hexabytes (2
52
)
64-bit Data and 32-bit Address Bus Interface
32 KB Instruction and Data Cache
Eight Independent Execution Units and Three Register Files
Write-back and Write-through Operations
f
INT
Max = 450 MHz (500 MHz to be confirmed)
f
BUS
Max = 133 MHz
Description
The PC7410 is the second microprocessor that uses the fourth (G4) full implementa-
tion of the PowerPC
™
Reduced Instruction Set Computer (RISC) architecture. It is
fully JTAG-compliant.
The PC7410 maintains some of the characteristics of G3 microprocessors:
•
•
•
The design is superscalar, capable of issuing three instructions per clock cycle
into eight independent execution units
The microprocessor provides four software controllable power-saving modes and
a thermal assist unit management
The microprocessor has separate 32-Kbyte, physically-addressed instruction and
data caches with dedicated L2 cache interface with on-chip L2 tags
PowerPC 7410
RISC
Microprocessor
Preliminary
Specification
α-site
PC7410
In addition, the PC7410 integrates full hardware-based multiprocessing capability,
including a 5-state cache coherency protocol (4 MESI states plus a fifth state for
shared intervention) and an implementation of the new AltiVec
™
technology instruc-
tion set.
New features have been developed to make latency equal for double-precision and
single-precision floating-point operations involving multiplication. Additionally, in mem-
ory subsystem (MSS) bandwidth, the PC7410 offers an optional, high-bandwidth MPX
bus interface.
Unlike the PC7400, the PC7410 does not support the 3.3V I/O on the L2 cache
interface.
Screening
•
•
•
CBGA Upscreenings Based on Atmel Standards
Full Military Temperature Range (T
j
= -55°C, +125°C),
Industrial Temperature Range (T
j
= -40°C, +110°C)
CI-CGA Package Versions
Rev. 2141A–HIREL–03/02
1
Block Diagram
Figure 1.
PC7410 Microprocessor Block Diagram
2
128 bits
(4 instructions)
Instruction MMU
Instruction Unit
SRs
(Shadow)
128-entry
ITLB
IBAT
Array
Tags
32-Kbyte
iCache
Fetcher
Branch Processing Unit
64-entry BTIC/512-entry BHT
LR/CTR
Data MMU
Dispatch Unit
EA
PC7410
Instruction
Queue
6-word
SRs
(Original)
Tags
PA
Additional features
Time Base
Counter/Decrementer
Clock Multiplier
JTAG/COP Interface
Thermal/Power Management
Performance Monitor
2 Instructions
128-entry
DTLB
DBAT
Array
32-Kbyte
DCache
64-bit
(2 Instructions)
Reservation
Station
Reservation
Station
Reservation
Station
VR File
6 Rename
Buffers
6 Rename
Buffers
32-bit
Reservation
Station
Reservation
Station
GPR File
Reservation
Station
2-entry
FPR File
6 Rename
Buffers
Reservation
Station
Load/Store
Unit
- Add -
EA Calculation
Vector
Permute
Unit
Vector
ALU
Add-Multiply-
divide
- Add -
Integer
Unit 1
Integer
Unit 2
System
Register
Unit
Finished Stores
Completed
Stores
64-bit
Floating
64-bit
Point Unit
Add-Multiply-
divide
VSIU VCIU VFPU
FPSCR
32-bit
128-bit
32-bit
VSCR
128-bit
128 bits
Completion Unit
L2 Controller
L2 Data
L2 Tags
Transaction
L2CR
Queue
L2PMCR
L2 Castout
19-bit L2 Address Bus
64- or 32-bit L2 Data Bus
32-bit Address Bus
64-bit Data Bus
8-entry
Reorder Buffer
Bus Interface Unit
L2 Miss
Data
Transaction
Queue
Memory Subsystem
Data Reload Data Reload
Buffer
Table
2141A–HIREL–03/02
Instruction
Instruction
Reload Buffer Reload Table
PC7410
General Parameters
Table 1 provides a summary of the general parameters of the PC7410.
Table 1.
Device Parameters
Parameter
Technology
Die size
Transistor count
Logic design
Packages
Core power supply
I/O power supply
Description
0.18 µm CMOS, six-layer metal
6.32 mm x 8.26 mm (52 mm
2
)
10.5 million
Fully-static
Surface-mount, ceramic 360-ball or -column grid array
(CBGA/CI-CGA)
1.8V ± 100 mV dc or 1.5V ± 50 mV dc (nominal; see Table 4 for
Recommended Operating Conditions)
1.8V ± 100 mV dc or
2.5V ± 100 mV dc (input thresholds are configuration pin selectable) or
3.3V ± 100 mV (603 bus only)
(1)
Note:
1. 3.3V I/O bus not supported for 1.5V core power supply processor version.
Features
This section summarizes features of the PC7410’s implementation of the PowerPC
architecture. Major features of the PC7410 are as follows:
•
Branch Processing Unit
–
–
–
–
–
•
Four instructions fetched per clock
One branch processed per cycle (plus resolving two speculations)
Up to one speculative stream in execution, one additional speculative
stream in fetch
512-entry branch history table (BHT) for dynamic prediction
64-entry, 4-way set associative branch target instruction cache (BTIC) for
eliminating branch delay slots
Full hardware detection of dependencies (resolved in the execution units)
Dispatch two instructions to eight independent units (system, branch,
load/store, fixed-point unit 1, fixed-point unit 2, floating-point, AltiVec
permute, AltiVec ALU)
Serialization control (predispatch, postdispatch, execution serialization)
Register file access
Forwarding control
Partial instruction decode
8-entry completion buffer
Instruction tracking and peak completion of two instructions per cycle
Completion of instructions in program order while supporting out-of-order
instruction execution, completion serialization and all instruction flow
changes
Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
3
Dispatch Unit
–
–
–
•
–
–
–
•
–
–
–
Decode
Completion
•
Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands
–
2141A–HIREL–03/02
–
–
–
–
•
–
–
–
–
–
•
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–
•
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–
Fixed-point unit 2 (FXU2)—shift, rotate, arithmetic, logical
Single-cycle arithmetic, shifts, rotates, logical
Multiply and divide support (multi-cycle)
Early out multiply
Support for IEEE-754 standard single- and double-precision floating-point
arithmetic
Three-cycle latency, one-cycle throughput (single or double precision)
Hardware support for divide
Hardware support for denormalized numbers
Time deterministic non-IEEE mode
Executes CR logical instructions and miscellaneous system instructions
Special register transfer instructions
Full 128-bit data paths
Two dispatchable units: vector permute unit and vector ALU unit
Contains its own 32-entry 128-bit vector register file (VRF) with six renames
The vector ALU unit is further sub-divided into the vector simple integer unit
(VSIU), the vector complex integer unit (VCIU) and the vector floating-point
unit (VFPU).
Fully pipelined
One-cycle load or store cache access (byte, half-word, word, double-word)
Two-cycle load latency with one-cycle throughput
Effective address generation
Hits under misses (multiple outstanding misses)
Single-cycle unaligned access within double-word boundary
Alignment, zero padding, sign extend for integer register file
Floating-point internal format conversion (alignment, normalization)
Sequencing for load/store multiples and string operations
Store gathering
Executes the cache and TLB instructions
Big- and little-endian byte addressing supported
Misaligned little-endian supported
Supports FXU, FPU, and AltiVec load/store traffic
Complete support for all four architecture AltiVec DST streams
32K 32-byte line, 8-way set associative instruction cache (iL1)
32K 32-byte line, 8-way set associative data cache (dL1)
Single-cycle cache access
Pseudo least-recently-used (LRU) replacement
Data cache supports AltiVec LRU and transient instructions algorithm
Copy-back or write-through data cache (on a page-per-page basis)
Three-stage Floating-point Unit and a 32-entry FPR File
System Unit
AltiVec Unit
–
•
–
–
–
–
–
–
–
–
–
–
–
–
–
–
•
–
–
–
–
–
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4
Load/Store Unit
Level 1 (L1) Cache Structure
PC7410
2141A–HIREL–03/02
PC7410
–
–
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–
•
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Supports all PowerPC memory coherency modes
Non-blocking instruction and data cache
Separate copy of data cache tags for efficient snooping
No snooping of instruction cache except for ICBI instruction
Internal L2 cache controller and tags; external data SRAMs
512K, 1M and 2-Mbyte 2-way set associative L2 cache support
Copyback or write-through data cache (on a page basis or for all L2)
32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size
Supports pipelined (register-register) synchronous burst SRAMs and
pipelined (register-register) late-write synchronous burst SRAMs
Supports direct mapped mode for 256K, 512K, 1M or 2 Mbytes of SRAM
(either all, half or none of L2 SRAM must be configured as direct mapped.
Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4
supported
64-bit data bus which also support 32-bits bus mode
Selectable interface voltages of 1.8V and 2.5V
128 entry, 2-way set associative instruction TLB
128 entry, 2-way set associative data TLB
Hardware reload for TLBs
Four instruction BATs and four data BATs
Virtual memory support for up to four petabytes (2
52
) of virtual memory
Real memory support for up to four gigabytes (2
32
) of physical memory
Snooped and invalidated for TLBI instructions
All data buses between VRF, load/store unit, dL1, iL1, L2 and the bus are
128 bits wide
dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF
L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s
Up to eight outstanding out-of-order cache misses between dL1 and L2/bus
Up to seven outstanding out-of-order transactions on the bus
Load folding to fold new dL1 misses into older outstanding load and store
misses to the same line
Store miss merging for multiple store misses to the same line. Only
coherency action taken (i.e., address only) for store misses merged to all 32
bytes of a cache line (no data tenure needed).
Two-entry finished store queue and four-entry completed store queue
between load/store unit and dL1
Separate additional queues for efficient buffering of outbound data (castouts,
write throughs, etc.) from dL1 and L2
MPX bus extension to 60X processor interface
Mode-compatible with 60x processor interface
32-bit address bus
Level 2 (L2) Cache Interface
Memory Management Unit
Efficient Data Flow
–
–
•
Bus Interface
–
–
–
5
2141A–HIREL–03/02
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PCX7410VGSU500NE Related Products

PCX7410VGSU500NE PCX7410MGSU500NE PCX7410MGSU450NE
Description RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360 RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360 RISC Microprocessor, 32-Bit, 450MHz, CMOS, CBGA360
Maker Microchip Microchip Microchip
package instruction COLUMN INTERPOSER, CERAMIC, CGA-360 COLUMN INTERPOSER, CERAMIC, CGA-360 COLUMN INTERPOSER, CERAMIC, CGA-360
Reach Compliance Code unknown unknown unknown
ECCN code 3A001.A.3 3A001.A.2.C 3A001.A.2.C
Address bus width 32 32 32
bit size 32 32 32
boundary scan YES YES YES
maximum clock frequency 133 MHz 133 MHz 133 MHz
External data bus width 64 64 64
Format FLOATING POINT FLOATING POINT FLOATING POINT
Integrated cache YES YES YES
JESD-30 code S-CBGA-X360 S-CBGA-X360 S-CBGA-X360
length 25 mm 25 mm 25 mm
low power mode YES YES YES
Number of terminals 360 360 360
Package body material CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
encapsulated code CGA CGA CGA
Package shape SQUARE SQUARE SQUARE
Package form GRID ARRAY GRID ARRAY GRID ARRAY
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 4.2 mm 4.2 mm 4.2 mm
speed 500 MHz 500 MHz 450 MHz
Maximum supply voltage 1.55 V 1.55 V 1.55 V
Minimum supply voltage 1.45 V 1.45 V 1.45 V
Nominal supply voltage 1.5 V 1.5 V 1.5 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Terminal form UNSPECIFIED UNSPECIFIED UNSPECIFIED
Terminal pitch 1.27 mm 1.27 mm 1.27 mm
Terminal location BOTTOM BOTTOM BOTTOM
width 25 mm 25 mm 25 mm
uPs/uCs/peripheral integrated circuit type MICROPROCESSOR, RISC MICROPROCESSOR, RISC MICROPROCESSOR, RISC
Maximum operating temperature - 125 °C 125 °C
Minimum operating temperature - -55 °C -55 °C
Temperature level - MILITARY MILITARY

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