Unbuffered SoDIMM
DDR3 SDRAM
DDR3 SDRAM Specification
204pin Unbuffered SODIMM based on 1Gb D-die
64-bit Non-ECC
82FBGA with Lead-Free
(RoHS compliant)
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* Samsung Electronics reserves the right to change products or specification without notice.
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Unbuffered SoDIMM
Table Contents
DDR3 SDRAM
1.0 DDR3 Unbuffered SoDIMM Ordering Information ......................................................................................................4
2.0 Key Features .................................................................................................................................................................4
3.0 Address Configuration ................................................................................................................................................. 4
4.0 x64 DIMM Pin Configurations (Front side/Back side) ................................................................................................5
5.0 Pin Description ..............................................................................................................................................................6
6.0 Input/Output Functional Description ..........................................................................................................................7
7.0 Functional Block Diagram: ..........................................................................................................................................8
7.1 512MB, 64Mx64 Module(Populated as 1 rank of x16 DDR3 SDRAMs) ...............................................................8
7.2 1GB, 128Mx64 Module(Populated as 2 ranks of x16 DDR3 SDRAMs) ...............................................................9
7.3 2GB, 256Mx64 Module(Populated as 2 ranks of x8 DDR3 SDRAMs) ...............................................................10
8.0 Absolute Maximum Ratings .......................................................................................................................................11
8.1 Absolute Maximum DC Ratings ...........................................................................................................................11
8.2 DRAM Component Operating Temperature Range ............................................................................................11
9.0 AC & DC Operating Conditions .................................................................................................................................11
9.1 Recommended DC Operating Conditions (SSTL - 15) .......................................................................................11
10.0 AC & DC Input Measurement Levels .......................................................................................................................12
10.1 AC and DC Logic Input Levels for Single-ended Signals ................................................................................12
10.2 VREF Tolerances. ...............................................................................................................................................13
10.3 AC and DC Logic Input Levels for Differential Signals ...................................................................................14
10.3.1 Differential Signals Definition .................................................................................................................14
10.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ..................................14
10.3.3 Single-ended Requirements for Differential Signals ............................................................................15
10.3.4 Differential Input Cross Point Voltage ...................................................................................................16
10.4 Slew Rate Definition for Single Ended Input Signals ......................................................................................16
10.5 Slew rate definition for Differential Input Signals ............................................................................................16
11.0 AC and DC Output Measurement Levels ................................................................................................................17
11.1 Single Ended AC and DC Output Levels ..........................................................................................................17
11.2 Differential AC and DC Output Levels ..............................................................................................................17
11.3 Single Ended Output Slew Rate ........................................................................................................................17
11.4 Differential Output Slew Rate ............................................................................................................................18
12.0 IDD specification definition ......................................................................................................................................19
12.1 IDD SPEC Table ...................................................................................................................................................21
13.0 Input/Output Capacitance ........................................................................................................................................23
14.0 Electrical Characteristics and AC timing ................................................................................................................24
14.1 Refresh Parameters by Device Density .............................................................................................................24
14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin .........................................................24
14.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ..........................................................25
14.3.1 Speed Bin Table Notes ............................................................................................................................26
15.0 Timing Parameters for DDR3-800, DDR3-1066 and DDR3-1333 ............................................................................27
15.1 Jitter Notes ..........................................................................................................................................................30
15.2 Timing Parameter Notes .....................................................................................................................................31
15.3 Address / Command Setup, Hold and Derating: ..............................................................................................32
15.4 Data Setup, Hold and Slew Rate Derating: .......................................................................................................38
16.0 Physical Dimensions : .............................................................................................................................................43
16.1 64Mbx16 based 64Mx64 Module(1 Rank) .........................................................................................................43
16.2 64Mbx16 based 128Mx64 Module(2 Ranks) .....................................................................................................44
16.3 128Mbx8 based 256Mx64 Module(2 Ranks) .....................................................................................................45
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1.0 DDR3 Unbuffered SoDIMM Ordering Information
Part Number
M471B6474DZ1-CF7/F8/H9
M471B2874DZ1-CF7/F8/H9
M471B5673DZ1-CF7/F8/H9
DDR3 SDRAM
Density
512MB
1GB
2GB
Organization
64Mx64
128Mx64
256Mx64
Component Composition
64Mx16(K4B1G1646D-HC##)*4
64Mx16(K4B1G1646D-HC##)*8
128Mx8(K4B1G0846D-HC##)*16
Number of
Rank
1
2
2
Height
30mm
30mm
30mm
* ## : F7 / F8 / H9
** F7 : 800Mbps 6-6-6, F8 : 1066Mbps 7-7-7, H9 : 1333Mbps 9-9-9
2.0 Key Features
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
Unit
ns
tCK
ns
ns
ns
ns
JEDEC standard 1.5V ± 0.075V Power Supply
V
DDQ
= 1.5V ± 0.075V
400 MHz f
CK
for 800Mb/sec/pin, 533MHz f
CK
for 1066Mb/sec/pin, 667MHz f
CK
for 1333Mb/sec/pin
8 independent internal bank
Programmable CAS Latency: 6,7,8,9
Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 5(DDR3-800), 6(DDR3-1066), 7(DDR3-1333)
8-bit pre-fetch
Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
Bi-directional Differential Data Strobe
Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower than T
CASE
85
°
C, 3.9us at 85
°
C < T
CASE
< 95
°
C
Asynchronous Reset
3.0 Address Configuration
Organization
64x16(1Gb) based Module
128x8(1Gb) based Module
Row Address
A0-A12
A0-A13
Column Address
A0-A9
A0-A9
Bank Address
BA0-BA2
BA0-BA2
Auto Precharge
A10/AP
A10/AP
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Rev. 1.2 August 2008
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