MPC8555CVTAJFX datasheet, PDF - EEWORLD Datasheet

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MPC8555CVTAJFX: Description32-BIT, 533MHz, RISC PROCESSOR, PBGA783, 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，88 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MPC8555CVTAJFX Overview

32-BIT, 533MHz, RISC PROCESSOR, PBGA783, 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783

MPC8555CVTAJFX Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	BGA
package instruction	BGA,
Contacts	783
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	64
bit size	32
boundary scan	YES
maximum clock frequency	166 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B783
length	29 mm
low power mode	YES
Number of terminals	783
Maximum operating temperature	105 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	3.75 mm
speed	533 MHz
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	29 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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Freescale Semiconductor

Technical Data

MPC8555EEC

Rev. 4, 12/2006

MPC8555E PowerQUICC™ III

Integrated Communications Processor

Hardware Specifications

The MPC8555E integrates a PowerPC™ processor core

built on Power Architecture™ technology with system logic

required for networking, telecommunications, and wireless

infrastructure applications. The MPC8555E is a member of

the PowerQUICC™ III family of devices that combine

system-level support for industry-standard interfaces with

processors that implement the embedded category of the

Power Architecture technology. For functional

characteristics of the processor, refer to the

MPC8555E

PowerQUICC™ III Integrated Communications Processor

Reference Manual.

To locate any published errata or updates for this document

refer to http://www.freescale.com or contact your Freescale

sales office.

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Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 8

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12

Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 16

DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Ethernet: Three-Speed, MII Management . . . . . . . . . . 22

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . . 55

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

System Design Information . . . . . . . . . . . . . . . . . . . . . 77

Document Revision History . . . . . . . . . . . . . . . . . . . . 84

Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . 84

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