Data Sheet
FEATURES
8-/10-/12-Bit High Bandwidth
Multiplying DACs with Serial Interface
AD5426/AD5432/AD5443
GENERAL DESCRIPTION
The
AD5426/AD5432/AD5443
1
are CMOS 8-, 10-, and 12-bit
current output digital-to-analog converters (DACs), respectively.
These devices operate from a 2.5 V to 5.5 V power supply,
making them suitable for battery-powered applications and
many other applications.
These DACs use a double buffered, 3-wire serial interface that is
compatible with SPI, QSPI™, MICROWIRE, and most DSP
interface standards. In addition, a serial data out pin (SDO)
allows for daisy-chaining when multiple packages are used.
Data readback allows the user to read the contents of the DAC
register via the SDO pin. On power-up, the internal shift register
and latches are filled with 0s and the DAC outputs are at zero scale.
As a result of manufacturing on a CMOS submicron process,
the parts offer excellent 4-quadrant multiplication characteristics
with large signal multiplying bandwidths of 10 MHz. The applied
external reference input voltage, V
REF
, determines the full-scale
output current. An integrated feedback resistor, R
FB
, provides
temperature tracking and full-scale voltage output when combined
with an external current to voltage precision amplifier.
The
AD5426/AD5432/AD5443
DACs are available in small,
10-lead MSOPs.
The
EV-AD5443/46/53SDZ
evaluation board is available for
evaluating DAC performance. For more information, see the
UG-327
evaluation board user guide.
2.5 V to 5.5 V supply operation
50 MHz serial interface
10 MHz multiplying bandwidth
2.5 MSPS update rate
INL of ±1 LSB for 12-bit DAC
±10 V reference input
Low glitch energy < 2 nV-s
Extended temperature range −40°C to +125°C
10-lead MSOP
Pin-compatible 8-, 10-, and 12-bit current output DACs
Guaranteed monotonic
4-quadrant multiplication
Power-on reset with brownout detection
Daisy-chain mode
Readback function
0.4 µA typical power consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
V
DD
V
REF
FUNCTIONAL BLOCK DIAGRAM
AD5426/
AD5432/
AD5443
R
8-/10-/12-BIT
R-2R DAC
R
FB
I
OUT
1
I
OUT
2
DAC REGISTER
POWER-ON
RESET
INPUT LATCH
SYNC
SCLK
SDIN
CONTROL LOGIC AND
INPUT SHIFT REGISTER
SDO
03162-001
GND
Figure 1.
1
Protected by U.S. Patent No. 5,689,257.
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Rev. H
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AD5426/AD5432/AD5443
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Data Sheet
Circuit Operation ....................................................................... 15
Single-Supply Applications ....................................................... 17
Adding Gain ................................................................................ 17
DACs Used as a Divider or Programmable Gain Element ... 18
Reference Selection .................................................................... 18
Amplifier Selection .................................................................... 18
Serial Interface ............................................................................ 20
PCB Layout and Power Supply Decoupling................................ 22
Overview of the AD5426/AD5432/AD5443 and Related DACs .. 23
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
9/15—Rev. G to Rev. H
Deleted Positive Output Voltage Section and Figure 45;
Renumbered Sequentially.............................................................. 17
Changes to Adding Gain Section ................................................. 17
Changed Overview of AD54xx and AD55xx Devices Section
to Overview of the AD5426/AD5432/AD5443 and Related
DACs Section .................................................................................. 23
Changes to Ordering Guide .......................................................... 24
6/13—Rev. F to Rev. G
Change to General Description Section ........................................ 1
Changes to Ordering Guide .......................................................... 24
7/12—Rev. E to Rev. F
No Change to Content, Changed V
DD
Values in 7/12 Revision
History Only ...................................................................................... 2
7/12—Rev. D to Rev. E
Changed V
DD
= 3 V to V
DD
= 2.5 V ............................. Throughout
Changes to Table 2 ............................................................................ 4
Changes to Table 4 ............................................................................ 7
Change to Daisy-Chain Mode Section ........................................ 20
Change to Ordering Guide ............................................................ 24
4/12—Rev. C to Rev. D
Changed V
DD
= 2.5 V to V
DD
= 3 V ............................. Throughout
Changes to General Description Section ...................................... 1
Deleted Microprocessor Interface Section, ADSP-21xx to
AD5426/AD5432/AD5443 Interface Section, Figure 51,
Figure 52, Table 11, ADSP-BF5x to AD5426/AD5432/AD5443
Interface Section, Figure 53 and Figure 54; Renumbered
Sequentially ..................................................................................... 21
Deleted 80C51/80L51 to AD5426/AD5432/AD5443 Interface
Section, Figure 55, MC68HC11 Interface to AD5426/AD5432/
AD5443 Interface Section, Figure 56, MICROWIRE to
AD5426/AD5432/AD5443 Interface Section, Figure 57,
PIC16C6x/7x to AD5426/AD5432/AD5443, and Figure 58 .... 22
Deleted Evaluation Board for the AD5426/AD5432/AD5443
Series of DACs Section, Operating the Evaluation Board
Section, and Power Supplies Section ........................................... 23
Deleted Figure 59 and Figure 60................................................... 24
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
Deleted Figure 61............................................................................ 25
Deleted Figure 62............................................................................ 26
2/09—Rev. B to Rev. C
Changes to Low Power Serial Interface Section and Daisy-
Chain Mode Section....................................................................... 20
Updated Outline Dimensions ....................................................... 28
11/08—Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 28
5/05—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Specifications .................................................................3
Changes to Figure 42...................................................................... 16
Change to Figure 45 ....................................................................... 17
Change to Figure 46 ....................................................................... 18
Changes to Table 7, Table 8, and Table 9 ..................................... 19
Additions to Microprocessor Interface Section.......................... 21
2/04—Revision 0: Initial Version
Rev. H | Page 2 of 24
Data Sheet
SPECIFICATIONS
AD5426/AD5432/AD5443
V
DD
= 2.5 V to 5.5 V, V
REF
= 10 V, I
OUT
2 = 0 V; temperature range for Y version: −40°C to +125°C; all specifications T
MIN
to T
MAX
, unless
otherwise noted; dc performance measured with
OP177;
ac performance with
AD8038,
unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
AD5426
Resolution
Relative Accuracy
Differential Nonlinearity
AD5432
Resolution
Relative Accuracy
Differential Nonlinearity
AD5443
Resolution
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient
1
Output Leakage Current
REFERENCE INPUT
1
Reference Input Range
V
REF
Input Resistance
R
FB
Resistance
Input Capacitance
Code Zero Scale
Code Full Scale
DIGITAL INPUT/OUTPUT
1
Input High Voltage, V
IH
Input Low Voltage, V
IL
Output High Voltage, V
OH
Output Low Voltage, V
OL
Input Leakage Current, I
IL
Input Capacitance
DYNAMIC PERFORMANCE
1
Reference Multiplying Bandwidth
Output Voltage Settling Time
Measured to ±16 mV of FS
Measured to ±4 mV of FS
Measured to ±1 mV of FS
Digital Delay
10% to 90% Rise/Fall Time
Digital-to-Analog Glitch Impulse
Multiplying Feedthrough Error
Min
Typ
Max
Unit
Test Conditions/Comments
8
±0.25
±0.5
10
±0.5
±1
12
±1
−1/+2
±10
±5
±10
±20
±10
10
10
3
5
1.7
0.6
V
DD
− 1
V
DD
− 0.5
0.4
0.4
1
10
Bits
LSB
LSB
Bits
LSB
LSB
Bits
LSB
LSB
mV
ppm FSR/°C
nA
nA
V
kΩ
kΩ
pF
pF
V
V
V
V
V
V
μA
pF
MHz
Guaranteed monotonic
Guaranteed monotonic
Guaranteed monotonic
Data = 0x0000, T
A
= 25°C, I
OUT
1
Data = 0x0000, T = −40°C to 125°C, I
OUT
1
8
8
12
12
6
8
Input resistance TC = −50 ppm/°C
Input resistance TC = −50 ppm/°C
V
DD
= 4.5 V to 5 V, I
SOURCE
= 200 μA
V
DD
= 2.5 V to 3.6 V, I
SOURCE
= 200 μA
V
DD
= 4.5 V to 5 V, I
SINK
= 200 μA
V
DD
= 2.5 V to 3.6 V, I
SINK
= 200 μA
4
10
V
REF
= ±3.5 V; DAC loaded all 1s
V
REF
= 10 V; R
LOAD
= 100 Ω, DAC latch alternately
loaded with 0s and 1s
50
55
90
40
15
2
70
48
100
110
160
75
30
ns
ns
ns
ns
ns
nV-s
dB
dB
Interface delay time
Rise and fall time, V
REF
= 10 V, R
LOAD
= 100 Ω
1 LSB change around major carry, V
REF
= 0 V
DAC latch loaded with all 0s, V
REF
= ±3.5
1 MHz
10 MHz
Rev. H | Page 3 of 24
AD5426/AD5432/AD5443
Parameter
Output Capacitance
I
OUT
1
I
OUT
2
Digital Feedthrough
Analog THD
Digital THD
50 kHz f
OUT
20 kHz f
OUT
Output Noise Spectral Density
SFDR Performance (Wide Band)
50 kHz f
OUT
20 kHz f
OUT
SFDR Performance (Narrow Band)
50 kHz f
OUT
20 kHz f
OUT
Intermodulation Distortion
POWER REQUIREMENTS
Power Supply Range
I
DD
Power Supply Sensitivity
1
Data Sheet
Min
Typ
12
10
22
10
0.1
81
73
74
25
75
76
87
87
78
2.5
0.4
5.5
0.6
5
0.001
Max
17
12
25
12
Unit
pF
pF
pF
pF
nV-s
dB
dB
dB
nV/√Hz
dB
dB
Clock = 1 MHz, V
REF
= 3.5 V
dB
dB
dB
V
µA
µA
%/%
Test Conditions/Comments
All 0s loaded
All 1s loaded
All 0s loaded
All 1s loaded
Feedthrough to DAC output with SYNC high and
alternate loading of all 0s and all 1s
V
REF
= 3.5 V p-p, all 1s loaded, f = 1 kHz
Clock = 1 MHz, V
REF
= 3.5 V, C
COMP
= 1.8 pF
@ 1 kHz
Clock = 1 MHz, V
REF
= 3.5 V
Clock = 1 MHz, f
1
= 20 kHz, f
2
= 25 kHz, V
REF
= 3.5 V
1
T
A
= 25°C, logic inputs = 0 V or V
DD
T = −40°C to +125°C , logic inputs = 0 V or V
DD
∆V
DD
= ±5%
Guaranteed by design and characterization, not subject to production testing.
Rev. H | Page 4 of 24
Data Sheet
TIMING CHARACTERISTICS
AD5426/AD5432/AD5443
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. V
DD
= 2.5 V to 5.5 V,
V
REF
= 10 V, I
OUT
2 = 0 V; temperature range for Y version: −40°C to +125°C; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
f
SCLK
t
1
t
2
t
3
t
4 1
t
5
t
6
t
7
t
8
t
9 2, 3
1
2
2.5 V to 5.5 V
50
20
8
8
13
5
3
5
30
80
120
4.5 V to 5.5 V
50
20
8
8
13
5
3
5
30
45
65
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns max
Test Conditions/Comments
Max clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK active edge setup time
Data setup time
Data hold time
SYNC rising edge to SCLK active edge
Minimum SYNC high time
SCLK active edge to SDO valid
Falling or rising edge as determined by control bits of serial word.
Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with load circuit, as shown in Figure 4.
3
SDO operates with a VDD of 3.0 V to 5.5 V.
t
1
SCLK
t
8
SYNC
t
4
t
2
t
3
t
7
t
6
t
5
DIN
DB15
DB0
03162-002
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF
SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED.
Figure 2. Standalone Mode Timing Diagram
t
1
SCLK
t
2
t
4
SYNC
t6
t
3
t
7
t
8
t
5
SDIN
DB15 (N)
t
6
DB0 (N)
DB15½
(N + 1)
DB0
(N + 1)
t
9
SDO
DB15(N)
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED.
DB0(N)
03162-003
Figure 3. Daisy-Chain and Readback Modes Timing Diagram
Rev. H | Page 5 of 24
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