Am29F002B/Am29F002NB
Data Sheet
J uly 2 003
The following docu ment specifies Spansion mem ory products that ar e n ow offered by both Advanced
Micro Devices and Fu jitsu . Although the d ocu ment is marked with the nam e of the company that orig-
inally developed the specification, th ese pro ducts will b e offered to cus tomers of both AM D and
Fujitsu.
Continuity of Specifications
There is no change to th is datasheet as a result of offer ing the device as a Spansion produ ct. Any
changes that have been m ade are the result of normal datasheet im provement an d are noted in the
docum en t revision sum mary, wh er e suppor ted. Future routine r evisions will occur when appropriate,
and changes will be noted in a revision s umm ar y.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to s upport existing p ar t nu mbers beginning with “Am” and “MBM”. To order
these products, please use only the O rderin g Part Num bers listed in this document.
For More Information
Please contac t your local AMD or Fuj its u s ales offic e for additional in for mation abou t Span sion
m em ory solutions.
Public atio n Number
21527
R evisio n
D
Amendment +
1
Issue D ate
N ovemb er 5, 200 4
T HIS PAGE L EFT INTENTIONALLY BLANK.
Am29F002B/Am29F002NB
2 Megabit (256 K x 8-Bit)
CMOS 5.0 Volt-only Boot Sector Flash Mem ory
DISTINCTIVE CHARACTERIST ICS
■
S ingle powe r supply operation
— 5.0 Volt-o nly op era tio n fo r rea d, e rase, an d
pr ogra m ope ratio ns
— Min imizes system level re qu ireme nts
■
Ma nuf act ure d on 0.32 µm proce ss t echnology
— Com patibl e with 0.5 µm Am2 9F00 2 device
■
High pe rform ance
— A cce ss times as fa st as 55 n s
■
Low powe r c ons umption (ty pic al v alues at
5 MHz)
— 1 µ A sta ndb y mo de cur ren t
— 20 mA rea d curr ent
— 30 mA pro gra m/e rase cur ren t
■
Flexible sec tor a rc hit ect ure
— O ne 16 Kbyte, two 8 K byte , on e 32 K byte, a nd
thre e 64 K byte se cto rs
— S upp or ts full chip erase
— S ecto r Pro tecti on featur es:
A h ard wa re me th od o f lo ckin g a sector to
pr eve nt any pro gra m o r erase o pe ration s withi n
tha t sector
Sectors can b e locked via programming eq uipme nt
Temp ora ry Se cto r Unpr otect fea tu re a llows code
cha nge s i n previo usly locked sectors
■
Top or bottom boot block configura tions availa ble
■
E mbe dded Algorithms
— E mbe dde d Er ase alg or ith m autom atically
p rep rog rams an d era se s the entire ch ip or a ny
co mbin ation o f d esign ated sector s
— E mbe dde d Pr ogra m alg orith m a utoma ti ca lly
wr ites and ver ifies data a t spe cifi ed ad dre sse s
■
Minimum 1 ,000 ,0 00 w rit e cycle guara ntee pe r
s ec tor
■
2 0-y ear dat a re tent ion at 12 5
°
C
— Re liab le op era tio n fo r th e life of the system
■
P ack age option
— 3 2-p in PDIP
— 3 2-p in TSO P
— 3 2-p in PL CC
■
Com patibility with JEDE C sta nda rds
— P ino ut and so ftwar e co mpa ti ble with
sin gle-po we r supp ly Fl ash
— S up eri or ina dver te nt write pr otection
■
Da ta# Polling a nd toggle bit s
— P rovid es a softwa re metho d of dete ctin g
p rog ram or e rase o pera tion comp letio n
■
E rase Suspe nd/E ra se Re sum e
— S uspe nd s an era se op era ti on to re ad data fr om,
o r pro gra m d ata to, a sector tha t is not be ing
e rase d, the n resu mes th e era se op eratio n
■
Ha rdw are rese t pin (RE SE T#)
— Ha rdwa re metho d to rese t th e device to r ead ing
a rray da ta ( not availa ble on Am29 F00 2NB)
Pu bl ic a tio n #
2 1 52 7
R e v:
D
Am e nd m e nt/
1
Is su e D ate :
N ove m be r 5, 2 0 04
R efe r to AM D’s Website (w ww.amd.c om) for the latest inform ation.
GENERAL DESCRIPTION
T h e A m2 9 F0 0 2 B F a mi l y c o n si s ts o f 2 M b it , 5 .0
vol t-o nly Fla sh memo ry d evices o rga nized as 262 ,144
b yte s. The A m2 9F00 2B o ffe rs th e RES ET# fu nctio n,
th e A m 2 9F 00 2 NB d oe s n o t. T h e d a ta a p pe a r s on
DQ 7 – DQ 0 . Th e d e vic e i s offe r ed in 3 2- p in P LC C,
3 2-p in TSO P, an d 32 -pi n PDIP p ackag es. Th is device
is d esig ned to be pro gra mmed in- system with the stan-
d ard system 5.0 vo lt V
C C
supp ly. No V
PP
is req uire d for
wri te o r era se op era tio ns. The de vice can a lso be p ro-
g ramme d in stand ard E PRO M pro gra mmers.
Th is d evi ce i s ma nu fac tur ed us in g A MD’s 0 .3 2 µ m
p rocess techn olo gy, and offe rs all th e featur es an d b en-
e fits of th e Am2 9F00 2, which was man ufa ctu red using
0 .5 µ m p roce ss techn olo gy.
The sta nda rd de vi ce o ffer s a cce ss times of 55 , 70 , 9 0,
a nd 1 20 n s, all owin g hi gh spe ed m icro pro cesso rs to
o pera te witho ut wait sta tes. To elimi nate b us con te ntion
th e de vi ce ha s se p a ra te ch ip e n ab l e (CE # ) , w r ite
e nabl e (WE #) an d ou tp ut e na ble ( O E#) co ntro ls.
Th e de vic e r eq u ir e s on l y a
s ingle 5.0 vo lt pow e r
s upply
for b o th re ad a n d wr ite fu ncti on s. In ter n all y
g ene rated and reg ula ted volta ges a re p rovide d for the
p rogr am an d era se o pe ration s.
The device is en ti rely co mmand set comp atible with the
J EDE C single-pow er- supply Flas h st andard.
Com-
m an d s a re wr it ten to the co mm a nd re g i ste r u si ng
stan da rd micro pro cesso r wr ite ti ming s. Reg ister con -
ten ts ser ve as inp ut to an in te rn al sta te -ma chin e th at
co ntr ol s th e er ase a n d pr og ra mmi ng ci rcu itr y. W rite
cycles a lso i nter nal ly latch add resse s and d ata n ee ded
for the pro gr amm ing a n d era se op e ratio n s. Rea di ng
d ata o ut o f th e device is simil ar to re adi ng fr om other
Fla sh or EP ROM device s.
Device p rog rammi ng o ccu rs by exe cu ting the pro gra m
co mm a nd se qu e nc e. Th is i ni tia te s th e
E m be dde d
P rogra m
a lgo ri th m— an i nter na l alg or ith m tha t a uto -
ma ti ca lly time s the p rogr am pul se wid ths a nd veri fie s
p rop er cell ma rgin .
D e vi c e e r a s u r e o cc u r s b y ex e c u ti n g th e e r a se
co mm a nd se qu e nc e. Th is i ni tia te s th e
E m be dde d
E rase
a lgo rithm— an in te rn al alg orith m that autom ati-
c a l l y p r e p r o g r a ms th e a r r a y ( i f i t is n o t a l r e a d y
p ro gr am med ) b efor e exe cutin g th e er ase o pe ra tio n.
Du rin g era se, the d evice auto matically times th e era se
p ulse wid ths a nd ver ifies pro per ce ll marg in.
T he ho st syste m ca n d ete ct wh e the r a p r og ra m o r
e rase ope ratio n is com plete by rea din g the DQ7 (Da ta #
Po llin g) an d DQ6 (to ggle )
sta tus bit s.
After a pr ogr am
o r e rase cycle h as be en comp leted , th e d evice i s rea dy
to re ad a rray data o r accept an other co mman d.
Th e
s ect or erase archite cture
a llows me mor y sectors
to be e rased an d rep rog ramme d with ou t affe ctin g th e
d a ta c on te n ts of o th er se cto rs. Th e d e vic e is fu l ly
e rase d when sh ipp ed fro m the factor y.
Hardw are data prot ection
mea sure s inclu de a low VCC
d ete ctor th at a utoma tically in hibits write opera tions dur ing
p owe r tra nsiti on s. Th e
hardw are s ec tor prot ec tion
featur e di sa bles b oth pr ogram and era se op eration s in
a ny co mbination of the se ctors of memor y. This can be
a chieved via progra mmin g eq uipment.
Th e
Era se S uspe nd
fea tu re e nab les the use r to p ut
e rase o n ho ld for an y p eri od o f time to re ad d ata from,
o r p rog ram data to, a ny se ctor that i s no t se lected fo r
e rasu re. Tru e ba ckgr oun d era se ca n th us be ach ieved.
Th e
ha rdw are RE SE T# pin
ter mina te s an y ope ratio n
i n pr og ress an d re sets th e in ter na l sta te mach in e to
r ead ing a rray data . The RE SE T# p in can b e tie d to th e
system re set circui tr y. A syste m rese t wo uld th us a lso
r eset the d evice, en abli ng th e system microp roce sso r
to re ad the bo ot-up firm wa re from th e Flash memo ry.
( This fea ture is no t avail able o n the A m29F0 02 NB.)
Th e system can place the device into th e
standby mode
.
Power co nsu mp tion is grea tly re duced in this mode.
A M D’s Fl a sh tec hn o lo g y co mb in e s ye a rs o f Fl as h
m e mo r y ma n ufa ctu r in g e xp er ie n ce t o p ro d uc e th e
h ighe st levels of qua lity, relia bility a nd cost effectiven ess.
Th e de vice ele ctrica lly er ases al l b its wi th in a se cto r
s imu lta ne ou sly via Fo wl er -No rd he im tu nn el in g. Th e
d ata is pro gra mmed u si ng ho t e lectron i njectio n.
2
Am 29 F002 B/Am 29 F00 2NB
TABLE OF CONTENTS
P roduc t S elec tor G uide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connec tion Diagram s . . . . . . . . . . . . . . . . . . . . . . 6
P in Configura tion. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Sy mbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
O rde ring Inf orm at ion . . . . . . . . . . . . . . . . . . . . . . .8
De vice Bus O perations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Am29F002B/Am29F 002NB Device Bus Oper ations . . . . . .9
Requirement s for Reading Array Dat a . . . . . . . . . . . . . . . . . . 9
W riting Commands/Command Sequences . . . . . . . . . . . . . . . 9
Program and E rase Operat ion S tat us . . . . . . . . . . . . . . . . . . . 9
St andby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RESE T#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . 10
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2. Am29F002B/Am29F002NB Top Boot Block Sector
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 3. Am29F002B/Am29F002NB Bottom Boot Block Sector
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Am29F002B/Am29F002NB Autoselect Codes (High
Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Sector P rotection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . 11
Temporary Sect or Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 1. Temporary Sector Unprotect Operation . . . . . . . . . . . . . .12
Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Low V
CC
Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Write Pulse “Glitch” Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Com ma nd De finitions . . . . . . . . . . . . . . . . . . . . . . 1 3
Reading Array Dat a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Autoselect Command S equence . . . . . . . . . . . . . . . . . . . . . . 13
Byt e P rogram Command Sequence . . . . . . . . . . . . . . . . . . . 13
Figure 2. Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . 14
Sector E rase Command Sequence . . . . . . . . . . . . . . . . . . . . 14
Figure 3. Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Erase Suspend/ Erase Resume Commands . . . . . . . . . . . . . 16
Command Definit ions ... ..... .... ..... ..... ..... .... ..... ..... ..... .... ..... ..... . 17
Table 5. Am29F002B/Am29F002NB Command Definitions . . . . . .17
Write O peration Sta tus . . . . . . . . . . . . . . . . . . . . . 1 8
DQ7: Data# P olling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4. Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 18
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . 19
DQ5: Exceeded Timing Limit s . . . . . . . . . . . . . . . . . . . . . . . . 19
DQ3: Sector E rase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 5. Toggle Bit Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Abs olut e Maxim um Rat ings . . . . . . . . . . . . . . . . 22
Figure 6. Maximum Negative Overshoot Waveform . . . . . . . . . . . 22
Figure 7. Maximum Positive Overshoot Waveform . . . . . . . . . . . . 22
O perat ing Range s . . . . . . . . . . . . . . . . . . . . . . . . 22
DC Chara cte rist ic s . . . . . . . . . . . . . . . . . . . . . . . . 23
Te st Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 7. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Ke y to Sw it ching Wa ve form s . . . . . . . . . . . . . . . 25
AC Chara cte rist ic s . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 9. Read Operations Timings . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 10. RESET# Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Program Operation Timings . . . . . . . . . . . . . . . . . . . . . 29
Figure 12. Chip/Sector Erase Operation Timings . . . . . . . . . . . . . 30
Figure 13. Data# Polling Timings (During Embedded Algorithms) . 31
Figure 14. Toggle Bit Timings (During Embedded Algorithms) . . . 31
Figure 15. DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. Temporary Sector Unprotect Timing Diagram
(Am29F002B only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 17. Alternate CE# Controlled Write Operation Timings . . . 34
E rase and P rogra mm ing P erforma nce . . . . . . . 35
La tchup Charac teristics . . . . . . . . . . . . . . . . . . . 35
TS OP Pin Ca pacita nce . . . . . . . . . . . . . . . . . . . . 35
P LCC and P DIP Pin Capac it ance . . . . . . . . . . . . 36
Da ta Re tention . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
P hys ic al Dim ensions . . . . . . . . . . . . . . . . . . . . . . 37
P D 032—32-P in Plastic DI P . . . . . . . . . . . . . . . . . . . . . . . . . 37
P L 032—32-Pin Plastic Leaded Chip Carrier . . . . . . . . . . . . 38
TS 032—32-P in St andard Thin S mall P ackage . . . . . . . . . . 39
Re vision Sum ma ry . . . . . . . . . . . . . . . . . . . . . . . . 40
Revision A (July 1998) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Revision B (January 1999) . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Revision C (November 12, 1999) . . . . . . . . . . . . . . . . . . . . . 40
Revision D (November 28, 2000) . . . . . . . . . . . . . . . . . . . . . 40
Am 29 F002 B/Am 29 F00 2NB
3
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