Rev. 1.01, Dec. 2009
K4B1G0446F
K4B1G0846F
1Gb F-die DDR3L SDRAM
78 FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
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K4B1G0446F
K4B1G0846F
datasheet
Rev. 1.01
DDR3L SDRAM
Table Of Contents
1Gb F-die DDR3L SDRAM
1. Ordering Information ..................................................................................................................................................... 5
2. Key Features................................................................................................................................................................. 5
3. Package pinout/Mechanical Dimension & Addressing.................................................................................................. 6
3.1 x4 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 6
3.2 x8 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 7
3.3 FBGA Package Dimension (x4/x8) .......................................................................................................................... 8
4. Input/Output Functional Description.............................................................................................................................. 9
5. DDR3 SDRAM Addressing ........................................................................................................................................... 10
6. Absolute Maximum Ratings .......................................................................................................................................... 11
6.1 Absolute Maximum DC Ratings............................................................................................................................... 11
6.2 DRAM Component Operating Temperature Range ................................................................................................ 11
7. AC & DC Operating Conditions..................................................................................................................................... 11
7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 11
8. AC & DC Input Measurement Levels ............................................................................................................................ 12
8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 12
8.2 V
REF
Tolerances...................................................................................................................................................... 13
8.3 AC & DC Logic Input Levels for Differential Signals ................................................................................................ 14
8.3.1. Differential signals definition ............................................................................................................................ 14
8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .................................................. 14
8.3.3. Single-ended requirements for differential signals ........................................................................................... 15
8.4 Differential Input Cross Point Voltage...................................................................................................................... 16
8.5 Slew rate definition for Differential Input Signals ..................................................................................................... 16
8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 16
9. AC & DC Output Measurement Levels ......................................................................................................................... 17
9.1 Single-ended AC & DC Output Levels..................................................................................................................... 17
9.2 Differential AC & DC Output Levels......................................................................................................................... 17
9.3 Single-ended Output Slew Rate .............................................................................................................................. 17
9.4 Differential Output Slew Rate .................................................................................................................................. 18
9.5 Reference Load for AC Timing and Output Slew Rate ............................................................................................ 18
9.6 Overshoot/Undershoot Specification ....................................................................................................................... 19
9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 19
9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 20
9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 20
9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 22
9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 22
9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 23
9.8.2. ODT Temperature and Voltage sensitivity ...................................................................................................... 25
9.9 ODT Timing Definitions ........................................................................................................................................... 26
9.9.1. Test Load for ODT Timings.............................................................................................................................. 26
9.9.2. ODT Timing Definitions .................................................................................................................................... 26
10. IDD Current Measure Method ..................................................................................................................................... 29
10.1 IDD Measurement Conditions ............................................................................................................................... 29
11. 1Gb DDR3L SDRAM F-die IDD Specification Table................................................................................................... 38
12. Input/Output Capacitance ........................................................................................................................................... 39
13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 ...................................................................... 40
13.1 Clock Specification ................................................................................................................................................ 40
13.1.1. Definition for tCK(avg).................................................................................................................................... 40
13.1.2. Definition for tCK(abs).................................................................................................................................... 40
13.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 40
13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 40
13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 40
13.1.6. Definition for tERR(nper)................................................................................................................................ 40
13.2 Refresh Parameters by Device Density................................................................................................................. 41
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 41
13.3.1. Speed Bin Table Notes44
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K4B1G0446F
K4B1G0846F
datasheet
DDR3L-1066 (7-7-7)
K4B1G0446F-HYF8
K4B1G0846F-HYF8
Rev. 1.01
DDR3L SDRAM
1. Ordering Information
[ Table 1 ] Samsung 1Gb DDR3L F-die ordering information table
Organization
256Mx4
128Mx8
NOTE
:
1. Speed bin is in order of CL-tRCD-tRP.
DDRL3-1333 (9-9-9)
K4B1G0446F-HYH9
K4B1G0846F-HYH9
Package
78 FBGA
78 FBGA
2. Key Features
[ Table 2 ] 1Gb DDR3 F-die Speed bins
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
DDR3-800
6-6-6
2.5
6
15
15
37.5
52.5
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
Unit
ns
nCK
ns
ns
ns
ns
• JEDEC standard 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
• V
DDQ
= 1.35V(1.28V~1.45V) & 1.5V(1.425V~1.575V)
• 400 MHz f
CK
for 800Mb/sec/pin, 533MHz f
CK
for 1066Mb/sec/pin,
667MHz f
CK
for 1333Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency(posted CAS): 6, 7, 8, 9
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800),
6 (DDR3-1066) and 7 (DDR3-1333)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting
address “000” only), 4 with tCCD = 4 which does not allow seamless
read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin
(RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than T
CASE
85°C, 3.9us at
85°C < T
CASE
< 95
°C
• Asynchronous Reset
• Package : 78 balls FBGA - x4/x8
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free
The 1Gb DDR3 SDRAM F-die is organized as a 32Mbit x 4 I/Os x 8banks,
16Mbit x 8 I/Os x 8banks device. This synchronous device achieves high
speed double-data-rate transfer rates of up to 1333Mb/sec/pin (DDR3-
1333) for general applications.
The chip is designed to comply with the following key DDR3 SDRAM fea-
tures such as posted CAS, Programmable CWL, Internal (Self) Calibration,
On Die Termination using ODT pin and Asynchronous Reset .
All of the control and address inputs are synchronized with a pair of exter-
nally supplied differential clocks. Inputs are latched at the crosspoint of dif-
ferential clocks (CK rising and CK falling). All I/Os are synchronized with a
pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-
ion. The address bus is used to convey row, column, and bank address
information in a RAS/CAS multiplexing style. The DDR3 device operates
with a single 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V) power supply
and 1.35V(1.28V~1.45V) or 1.5V(1.425V~1.575V).
The 1Gb DDR3 F-die device is available in 78ball FBGAs(x4/x8).
NOTE
: 1. This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing
Diagram”.
2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
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