FT29F080B-150SM datasheet, PDF

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FT29F080B-150SM: DescriptionFlash, 1MX8, 150ns, PDSO44, SOP-44; Categorystorage storage; File Size2MB，37 Pages; ManufacturerForce Technologies Ltd.

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FT29F080B-150SM Overview

Flash, 1MX8, 150ns, PDSO44, SOP-44

FT29F080B-150SM Parametric

Parameter Name	Attribute value
Maker	Force Technologies Ltd.
package instruction	SOP,
Reach Compliance Code	unknown
Maximum access time	150 ns
JESD-30 code	R-PDSO-G44
length	28.2 mm
memory density	8388608 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of terminals	44
word count	1048576 words
character code	1000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	1MX8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Programming voltage	5 V
Maximum seat height	2.8 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
type	NOR TYPE
width	13.3 mm

FT29F080B-150SM Preview

FT29F080B

8 Megabit (1 M x 8-Bit)

CMOS 5.0 Volt-only, Uniform Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

●

5.0 V

10%, single power supply operation

— Minimises system level power requirements

●

Minimum 1,000,000 program/erase cycles per

sector guaranteed

●

Manufactured on 0.32 µm process technology

— Compatible with 0.5 µm

FT29F080

device

●

20-year data retention at 125°C

— Reliable operation for the life of the system

●

High performance

— Access times as fast as

●

Package options

— 40-pin TSOP

— 44-pin SO

●

Low power consumption

— 25 mA typical active read current

— 30 mA typical program/erase current

— 1 µA typical standby current (standard access

time to active mode)

— Contact factory for ceramic package options

●

Compatible with JEDEC standards

— Pinout and software compatible with

single-power-supply Flash standard

— Superior inadvertent write protection

●

Flexible sector architecture

— 16 uniform sectors of 64 Kbytes each

— Any combination of sectors can be erased.

— Supports full chip erase

— Group sector protection:

A hardware method of locking sector groups to

prevent any program or erase operations within

that sector group

Temporary Sector Group Unprotect allows code

changes in previously locked sectors

●

Data# Polling and toggle bits

— Provides a software method of detecting program

or erase cycle completion

●

Ready/Busy# output (RY/BY#)

— Provides a hardware method for detecting

program or erase cycle completion

●

Erase Suspend/Erase Resume

— Suspends a sector erase operation to read data

from, or program data to, a non-erasing sector,

then resumes the erase operation

●

Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies bytes at specified addresses

●

Hardware reset pin (RESET#)

— Resets internal state machine to the read mode

●

Command sequence optimised for mass storage

— Specific addresses not required for unlock cycles

Rev. 1

1 of 37

July 2014

GENERAL DESCRIPTION

The

FT29F080B

is an 8 Mbit, 5.0 volt-only Flash mem-

ory organised as 1,048,576 bytes. The 8 bits of data

appear on DQ0–DQ7. The

FT29F080B

is offered in

40-pin TSOP and 44-pin SO packages. This device is

designed to be programmed in-system with the standard

system 5.0 volt V

supply. A 12.0 volt V

is not re-

quired for program or erase operations. The device can

also be programmed in standard EPROM programmers.

This device is manufactured using 0.32 µm

process technology, and offers all the features and ben-

efits of the

FT29F080,

which was manufactured using

0.5 µm process technology.

The standard device offers access times of 90,

120

and 150 ns, allowing high-speed microprocessors

to operate without wait states. To eliminate bus conten-

tion, the device has separate chip enable (CE#), write

enable (WE#), and output enable (OE#) controls.

The device requires only a

single 5.0 volt power sup-

ply

for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard.

Com-

mands are written to the command register using stan-

dard microprocessor write timings. Register contents

serve as input to an internal state-machine that con-

trols the erase and programming circuitry. Write cycles

also internally latch addresses and data needed for the

programming and erase operations. Reading data out

of the device is similar to reading from other Flash or

EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the

Embedded

Program

algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the

Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle)

status bits.

After a program or erase cycle has

been completed, the device is ready to read array data

or accept another command.

The

sector erase architecture

allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection

measures include a low

detector that automatically inhibits write opera-

tions during power transitions. The

hardware sector

protection

feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved via programming equipment.

The

Erase Suspend

feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The

hardware RESET# pin

terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The system can place the device into the

standby

mode.

Power consumption is greatly reduced in

this mode.

FT's

Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunneling.

The data is programmed using hot electron injection.

Rev. 1

2 of 37

July 2014

PRODUCT SELECTOR GUIDE

Family Part Number

Speed Option

Max Access Time, ns (t

ACC

)

Max CE# Access, ns (t

)

Max OE# Access, ns (t

)

FT29F080B

= 5.0 V

10%

-90

-120

120

-150

150

Note:

See the “AC Characteristics” section for more information.

BLOCK DIAGRAM

DQ0

–

DQ7

RY/BY#

RESET#

State

Control

Command

Sector Switches

Erase Voltage

Generator

Input/Output

Buffers

WE#

PGM Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Data

Latch

CE#

OE#

STB

Detector

Timer

Address Latch

Y-Decoder

Y-Gating

X-Decoder

Cell Matrix

A0–A19

Rev. 1

3 of 37

July 2014

CONNECTION DIAGRAMS

A19

A18

A17

A16

A15

A14

A13

A12

CE#

RESET#

A11

A10

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

40-Pin Standard TSOP

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

40-Pin Reverse TSOP

A19

A18

A17

A16

A15

A14

A13

A12

CE#

RESET#

A11

A10

RESET#

A11

A10

DQ0

DQ1

DQ2

DQ3

CE#

A12

A13

A14

A15

A16

A17

A18

A19

WE#

OE#

RY/BY#

DQ7

DQ6

DQ5

DQ4

Rev. 1

4 of 37

July 2014

PIN CONFIGURATION

A0–A19

CE#

WE#

OE#

RESET#

RY/BY#

20 Addresses

8 Data Inputs/Outputs

Chip Enable

Write Enable

Output Enable

Hardware Reset Pin, Active Low

Ready/Busy Output

+5.0 V single power supply

(see Product Selector Guide for

device speed ratings and voltage

supply tolerances)

Device Ground

Pin Not Connected Internally

DQ0–DQ7 =

LOGIC SYMBOL

A0–A19

DQ0–DQ7

CE#

OE#

WE#

RESET#

RY/BY#

Rev. 1

5 of 37

July 2014

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