FT6198(L)
FT6198A(L)
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 ns (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power Operation (Commercial/Military)
5V ± 10% Power Supply
Data Retention, 10
µA
Typical Current from 2.0V
FT6198L/FT6198AL
(Military)
Ultra High Speed 16K x 4
Static CMOS Ram
Output Enable & Chip Enable Control Functions
– Single Chip Enable
FT6198
– Dual Chip Enable
FT6198A
Common Inputs and Outputs
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 28-Pin 350 x 550 mil LCC
DESCRIPTION
The
FT6198/L
and
FT6198A/L
are 65,536-bit ultra high-
speed static RAMs organized as 16K x 4. Each device
features an active low Output Enable control to eliminate
data bus contention. The
FT6198/L
also have an active
low Chip Enable (the
FT6198A/L
have two Chip Enables,
both active low) for easy system expansion. The CMOS
memories require no clocks or refreshing and have equal
access and cycle times. Inputs are fully TTL-compatible.
The RAMs operate from a single 5V ± 10% tolerance
power supply. Data integrity is maintained with supply
voltages down to 2.0V. Current drain is typically 10
µA
from a 2.0V supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low 715
mW active, 193 mW standby.
The
FT6198/L
and
FT6198A/L
are available in 24-pin
300 mil DIP and SOJ, and 28-pin 350 x 550 mil LCC
packages providing excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
FT6198A ONLY
DIP (P4, C4, D4),
SOJ (J4)
FT6198
(FT6198A)
LCC (L5)
FT6198
(FT6198A)
REV 1
1/14
2008
FT6198(L)
FT6198A(L)
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
V
°C
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Military
Ambient
Temperature
GND
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions Typ. Unit
V
IN
= 0V
V
OUT
= 0V
5
7
pF
pF
–55°C to +125°C
0°C to +70°C
Commercial
–40°C to +85°C
Industrial
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
I
SB
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
V
CC
= Min., I
IN
= –18 mA
I
OL
= +10 mA, V
CC
= Min.
I
OL
= +8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
V
CC
= Max.,
CE
= V
IH
,
Mil.
Ind./Com’l.
Mil.
Ind./Com’l.
Test Conditions
FT6198
/
6198A
FT6198L
/
6198AL
Unit
Min
Max
Min
Max
2.2
V
CC
+0.5
V
CC
+0.5 V
2.2
–0.5
(3)
–0.5
(3)
0.5
0.4
2.4
–10
–5
–10
–5
___
___
___
___
+10
+5
+10
+5
40
35
20
15
2.4
–5
n/a
–5
n/a
___
___
___
___
+5
n/a
+5
n/a
40
n/a
1.5
n/a
0.8
0.2
–1.2
0.5
0.4
–0.5
(3)
–0.5
(3)
0.8
0.2
–1.2
V
V
V
V
V
V
V
µA
µA
mA
V
CC
–0.2 V
CC
+0.5 V
CC
–0.2 V
CC
+0.5
Mil.
CE
1
,
CE
2
≥
V
IH
Standby Power Supply
V
CC
= Max .,
Ind./Com’l.
Current (TTL Input Levels)
f = Max., Outputs Open
Standby Power Supply
Current
(CMOS Input Levels)
CE
1
,
CE
2
≥
V
IH
Mil.
Ind./Com’l.
V
CC
= Max.,
f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
mA
I
SB1
n/a = Not Applicable
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM ratingconditions for extended
periods may affect reliability.
REV 1
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
2/14
2008
FT6198(L)
FT6198A(L)
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Temperature
Range
Commercial
I
CC
Dynamic Operating Current*
Industrial
Military
198:
CE
= V
IL
,
OE
= V
IH
198A:
CE
1
= V
IL
,
CE
2
= V
IL
.
OE
= V
IH
–10
180
N/A
N/A
–12
170
180
N/A
–15
160
170
170
–20
155
160
160
–25
150
155
155
–35
N/A
150
150
–45
N/A
N/A
145
Unit
mA
mA
mA
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
DATA RETENTION CHARACTERISTICS (FT6198L/FT6198AL Military Temperature Only)
Symbol
V
DR
I
CCDR
t
CDR
t
R†
*
T
A
= +25°C
§
†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
Test Condition
Min
2.0
Typ.*
V
CC
=
2.0V
3.0V
10
15
Max
V
CC
=
2.0V
3.0V
600
900
Unit
V
µA
ns
ns
CE
≥V
CC
– 0.2V,
V
IN
≥
V
CC
– 0.2V or
V
IN
≤
0.2V
0
t
RC§
t
RC
= Read Cycle Time
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
(CE or CE
2
for the FT6198AL)
REV 1
3/14
2008
FT6198(L)
FT6198A(L)
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
-10
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
Parameter
Read Cycle Time
Address Access
Time
Chip Enable
Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable
Low to Data Valid
Output Enable to
Output in Low Z
2
6
0
10
0
2
2
6
6
2
10
10
10
2
2
12
-12
-15
15
12
12
2
2
7
7
2
7
0
12
15
9
0
8
9
2
15
15
2
2
20
-20
25
20
20
2
2
10
12
2
9
0
20
-25
35
25
25
2
2
10
15
2
10
0
25
-35
45
35
35
2
2
14
25
2
14
0
35
-45
ns
45
45
ns
ns
ns
ns
15
30
ns
ns
ns
15
ns
ns
45
ns
Min Max Min
Max Min Max Min Max Min Max Min Max Min Max Unit
t
OHZ
Output Disable to
Output in High Z
t
PU
t
PD
Chip Enable to
Power Up Time
Chip Disable to
Power Down Time
READ CYCLE NO.1 (OE controlled)
(5)
OE
Notes:
5.
WE
is HIGH for READ cycle.
REV 1
4/14
2008
FT6198(L)
FT6198A(L)
READ CYCLE NO. 2 (ADDRESS Controlled)
(5,6)
READ CYCLE NO. 3 (CE
(12)
Controlled)
(5,7,8)
CE
Notes:
6.
CE
(CE
1
CE
2
for
FT6198A/L)
and
OE
are LOW READ cycle.
7.
OE
is LOW for the cycle.
8. ADDRESS must be valid prior to, or coincident with
CE
(CE
1
and
CE
2
for
FT6198A/L)
transition LOW.
9. Transition is measured ± 200mV from steady state voltage
prior to change, with loading as specified in Figure 1.
REV 1
5/14
10. Read Cycle Time is measured from the last valid address
to the first transitioning address.
11. Transitions caused by a chip enable control have similar
delays irrespective of whether
CE
1
or
CE
2
causes them
(FT6198A/L).
12.
CE
1
,
CE
2
for
FT6198A/L.
2008
FPGA/CPLD
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