AT25020A-10PA-2.7C datasheet, PDF

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AT25020A-10PA-2.7C: DescriptionEEPROM, 256X8, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001BA, DIP-8; Categorystorage storage; File Size464KB，17 Pages; ManufacturerAtmel (Microchip)

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AT25020A-10PA-2.7C Overview

EEPROM, 256X8, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001BA, DIP-8

AT25020A-10PA-2.7C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Atmel (Microchip)
Parts packaging code	DIP
package instruction	DIP, DIP8,.3
Contacts	8
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum clock frequency (fCLK)	5 MHz
Data retention time - minimum	100
Durability	1000000 Write/Erase Cycles
JESD-30 code	R-PDIP-T8
JESD-609 code	e0
length	9.271 mm
memory density	2048 bit
Memory IC Type	EEPROM
memory width	8
Humidity sensitivity level	1
Number of functions	1
Number of terminals	8
word count	256 words
character code	256
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	256X8
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP8,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	5.334 mm
Serial bus type	SPI
Maximum standby current	0.000005 A
Maximum slew rate	0.006 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Maximum write cycle time (tWC)	5 ms
write protect	HARDWARE/SOFTWARE

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Features

•

Serial Peripheral Interface (SPI) Compatible

•

Supports SPI Modes 0 (0,0) and 3 (1,1)

•

– Data Sheet Describes Mode 0 Operation

Medium-voltage and Standard-voltage Operation

– 5.0 (V

= 4.5V to 5.5V)

– 2.7 (V

= 2.7V to 5.5V)

5.0 MHz Clock Rate

8-byte Page Mode

Block Write Protection

– Protect 1/4, 1/2, or Entire Array

Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software

Data Protection

Self-timed Write Cycle (10 ms max)

High Reliability

– Endurance: One Million Write Cycles

– Data Retention: 100 Years

8-pin PDIP and 8-lead JEDEC SOIC Package

SPI Serial

Automotive

EEPROMs

1K (128 x 8)

2K (256 x 8)

4K (512 x 8)

Description

The AT25010A/020A/040A provides 1024/2048/4096 bits of serial electrically eras-

able programmable read-only memory (EEPROM) organized as 128/256/512 words of

8 bits each. The device is optimized for use in many automotive applications where

low-power and low-voltage operation are essential. The AT25010A/020A/040A is

available in space-saving 8-pin PDIP and 8-lead JEDEC SOIC packages.

The AT25010A/020A/040A is enabled through the Chip Select pin (CS) and accessed

via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO),

and Serial Clock (SCK). All programming cycles are completely self-timed, and no

separate erase cycle is required before write.

Block write protection is enabled by programming the status register with one of four

blocks of write protection. Separate Program Enable and Program Disable instructions

are provided for additional data protection. Hardware data protection is provided via

the WP pin to protect against inadvertent write attempts. The HOLD pin may be used

to suspend any serial communication without resetting the serial sequence.

Table 1.

Pin Configurations

Pin Name

SCK

GND

VCC

Function

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

Power Supply

AT25010A

AT25020A

AT25040A

8-lead

PDIP

GND

VCC

HOLD

SCK

SPI, 1K Serial

PROM

8-lead SOIC

C S

W P

G N D

C C

O L

C K

3402B-SEEPR-9/04

AT25010A/020A/040A

Serial Interface

Description

MASTER:

The device that generates the serial clock.

SLAVE:

Beca use the serial clock pin (SCK) is alw ays an in put, th e

AT25010A/020A/040A always operates as a slave.

TRANSMITTER/RECEIVER:

The AT25010A/020A/040A has separate pins designated

for data transmission (SO) and reception (SI).

MSB:

The Most Significant Bit (MSB) is the first bit transmitted and received.

SERIAL OP-CODE:

After the device is selected with CS going low, the first byte will be

received. This byte contains the op-code that defines the operations to be performed.

The op-code also contains address bit A8 in both the Read and Write instructions.

INVALID OP-CODE:

If an invalid op-code is received, no data will be shifted into the

AT25010A/020A/040A, and the serial output pin (SO) will remain in a high impedance

state until the falling edge of CS is detected again. This will reinitialize the serial

communication.

CHIP SELECT:

The AT25010A/020A/040A is selected when the CS pin is low. When

the device is not selected, data will not be accepted via the SI pin, and the serial output

pin (SO) will remain in a high impedance state.

H OLD :

Th e H O LD p in is u se d in co n jun ctio n w it h the C S pin to s e le ct th e

AT25010A/020A/040A. When the device is selected and a serial sequence is underway,

HOLD can be used to pause the serial communication with the master device without

resetting the serial sequence. To pause, the HOLD pin must be brought low while the

SCK pin is low. To resume serial communication, the HOLD pin is brought high while the

SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored

while the SO pin is in the high impedance state.

WRITE PROTECT:

The write protect pin (WP) will allow normal read/write operations

when held high. When the WP pin is brought low, all write operations are inhibited.

WP going low while CS is still low will interrupt a write to the AT25010A/020A/040A. If

the internal write cycle has already been initiated, WP going low will have no effect on

any write operation.

3402B-SEEPR-9/04

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