SO
T2
PHT4NQ10LT
N-channel TrenchMOS logic level FET
Rev. 2 — 28 October 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications.
23
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Logic level compatible
1.3 Applications
DC-to-DC converters
General purpose switching
High-speed line drivers
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
V
GS
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
gate-source voltage
drain-source on-state
resistance
V
GS
= 5 V; I
D
= 1.75 A; T
j
= 25 °C;
see
Figure 10;
see
Figure 11
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
sp
= 25 °C; V
GS
= 5 V; see
Figure 1;
see
Figure 2
Min
-
-
-16
-
Typ
-
-
-
200
Max
100
3.5
16
250
Unit
V
A
V
mΩ
Static characteristics
2. Pinning information
Table 2.
Pin
1
2
3
4
Pinning information
Symbol Description
G
D
S
D
gate
drain
source
drain
1
2
3
mbb076
Simplified outline
4
Graphic symbol
D
G
S
SOT223 (SC-73)
NXP Semiconductors
PHT4NQ10LT
N-channel TrenchMOS logic level FET
3. Ordering information
Table 3.
Ordering information
Package
Name
PHT4NQ10LT
SC-73
Description
plastic surface-mounted package with increased heatsink;
4 leads
Version
SOT223
Type number
4. Marking
Table 4.
Marking codes
Marking code
4NQ10L
Type number
PHT4NQ10LT
5. Limiting values
Table 5.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
sp
= 100 °C; V
GS
= 5 V
T
sp
= 25 °C; V
GS
= 5 V; see
Figure 1;
see
Figure 2
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
non-repetitive avalanche
current
T
sp
= 25 °C
T
sp
= 25 °C; pulsed; t
p
≤
10 µs
V
GS
= 5 V; T
j
= 25 °C; I
D
= 3.5 A;
R
GS
= 50
Ω;
V
sup
≤
15 V; unclamped;
t
p
= 0.2 ms; see
Figure 4
V
sup
≤
15 V; V
GS
= 5 V; T
j(init)
= 25 °C;
R
GS
= 50
Ω;
unclamped; see
Figure 4
T
sp
= 25 °C; pulsed; t
p
≤
10 µs;
see
Figure 1
T
sp
= 25 °C; see
Figure 3
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
j
≥
25 °C; T
j
≤
150 °C; R
GS
= 20 kΩ
Min
-
-
-16
-
-
-
-
-65
-65
-
-
-
Max
100
100
16
2.2
3.5
14
6.9
150
150
3.5
14
45
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
I
AS
-
3.5
A
PHT4NQ10LT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 28 October 2011
2 of 13
NXP Semiconductors
PHT4NQ10LT
N-channel TrenchMOS logic level FET
102
ID
(A)
10
RDSon = VDS/ ID
03ac48
120
I
der
(%)
80
03aa25
tp = 10 µs
100 µs
1
D.C.
10-1
P
1 ms
10 ms
100 ms
40
δ
=
tp
T
tp
t
T
10-2
1
0
10
102
VDS
103
0
50
100
150
T
sp
(°C)
200
Fig 1.
Safe operating area; continuous and peak drain
currents as a function of drain-source voltage
03aa17
Fig 2.
Normalized continuous drain current as a
function of solder point temperature
10
03ac92
120
P
der
(%)
80
I
AS
(A)
25°C
1
40
T
j
prior to avalanche = 125°C
0
0
50
100
150
T
sp
(°C)
200
10
−1
10
−2
10
−1
1
t
p
(ms)
10
Unclamped inductive load; V
DD
≤
15 V;
R
GS
= 50
Ω;
V
GS
= 5 V; starting T
j
= 25 °C and 125 °C.
Fig 3.
Normalized total power dissipation as a
function of solder point temperature
Fig 4.
Non-repetitive avalnche ruggednes current as a
function of pulse duration
PHT4NQ10LT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 28 October 2011
3 of 13
NXP Semiconductors
PHT4NQ10LT
N-channel TrenchMOS logic level FET
6. Thermal characteristics
Table 6.
Symbol
R
th(j-sp)
Thermal characteristics
Parameter
thermal resistance
from junction to solder
point
thermal resistance
from junction to
ambient
Conditions
mounted on a metal clad substrate
Min
-
Typ
-
Max
18
Unit
K/W
R
th(j-a)
mounted on a printed-circuit board ;
minimum footprint
-
-
150
K/W
102
Zth(j-sp)
(K/W)
10
d = 0.5
0.2
1
0.1
0.05
0.02
P
03ac84
δ
=
tp
T
10-1
single pulse
10-2
10-5
10-4
10-3
10-2
10-1
1
tp (s)
10
tp
T
t
T
sp
= 25 °C
Fig 5.
Transient thermal impedance from junction to solder point as a function of pulse duration
7. Characteristics
Table 7.
Symbol
V
(BR)DSS
V
GS(th)
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 150 °C;
see
Figure 9
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
see
Figure 9
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
see
Figure 9
I
GSS
gate leakage current
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
Min
89
100
0.6
-
1
-
-
Typ
-
130
-
-
-
10
10
Max
-
-
-
2.3
2
100
100
Unit
V
V
V
V
V
nA
nA
Static characteristics
PHT4NQ10LT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 28 October 2011
4 of 13
NXP Semiconductors
PHT4NQ10LT
N-channel TrenchMOS logic level FET
Table 7.
Symbol
R
DSon
Characteristics
…continued
Parameter
drain-source on-state
resistance
Conditions
V
GS
= 5 V; I
D
= 1.75 A; T
j
= 150 °C;
see
Figure 10;
see
Figure 11
V
GS
= 5 V; I
D
= 1.75 A; T
j
= 25 °C;
see
Figure 10;
see
Figure 11
Min
-
-
Typ
-
200
Max
575
250
Unit
mΩ
mΩ
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain charge
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
reverse recovery time
recovered charge
I
S
= 3.5 A; V
GS
= 0 V; T
j
= 25 °C;
see
Figure 13
I
S
= 3.5 A; dI
S
/dt = -100 A/µs;
V
GS
= 0 V; V
DS
= 30 V; T
j
= 25 °C
V
DS
= 50 V; R
L
= 15
Ω;
V
GS
= 5 V;
R
G(ext)
= 6
Ω;
T
j
= 25 °C
I
D
= 3.5 A; V
DS
= 80 V; V
GS
= 5 V;
T
j
= 25 °C; see
Figure 12
-
-
-
-
-
-
-
-
-
-
6.8
1.1
3.6
4
10
52
21
0.87
50
100
-
-
-
-
-
-
-
1.5
-
-
nC
nC
nC
ns
ns
ns
ns
V
ns
nC
Source-drain diode
10
I
D
9
(A)
8
7
6
5
4
3
T
j
= 25°C
03ac85
10
I
D
9
(A)
8
7
6
5
V
DS
> I
D
X R
DSon
03ac87
V
GS
= 5V
3V
2.8V
2.6V
4
3
150°C
2
T
j
= 25°C
2.4V
2
1
0
0
0.2 0.4 0.6 0.8
1
2.2V
2V
1.2 1.4 1.6 1.8
V
DS
(V)
2
1
0
0
0.5
1
1.5
2
2.5
3
3.5
4
V
GS
(V)
Fig 6.
Output characteristics: drain current as a
function of drain-source voltage; typical values
Fig 7.
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
PHT4NQ10LT
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 28 October 2011
5 of 13
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