THS4011IDG4 datasheet, PDF - EEWORLD Datasheet

THS4011IDG4: DescriptionOP-AMP, 8000 uV OFFSET-MAX, 200 MHz BAND WIDTH, CDIP8; Categorysemiconductor Analog mixed-signal IC; File Size1MB，36 Pages; ManufacturerNational Semiconductor（TI ）; Websitehttp://www.ti.com

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OP-AMP, 8000 uV OFFSET-MAX, 200 MHz BAND WIDTH, CDIP8

Parameter Name	Attribute value
Number of functions	1
Number of terminals	8
Maximum supply/operating voltage	16.5 V
Maximum operating temperature	125 Cel
Minimum operating temperature	-55 Cel
Rated supply voltage	15 V
Maximum negative supply voltage	-16.5 V
Rated negative supply voltage	-15 V
Rated bandwidth	200 kHz
Rated rotation rate	400 V/us
Maximum input offset voltage	8000 mV
Processing package description	Ceramic, DIP-8
state	ACTIVE
Craftsmanship	BIPOLAR
packaging shape	Rectangle
Package Size	IN-line
Terminal form	THROUGH-hole
Terminal spacing	2.54 mm
terminal coating	NOT SPECIFIED
Terminal location	pair
Packaging Materials	Ceramic, Glass-SEALED
Temperature level	MILITARY
Amplifier type	Operational Amplifier
Rated common mode rejection ratio	90 dB
Maximum input bias current IIB	8 uA

[Project source code] [Modelsim FAQ] Port 'xxxx' not found in the connected module: This article and design code were written by FPGA enthusiast Xiao Meige. Without the author's permission, this article is only allowed to be copied and reproduced on online forums, and the original au...; 小梅哥 FPGA/CPLD

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crc16 source code sharing: // Copyright 2007 Altera Corporation. All rights reserved. // Altera products are protected under numerous U.S. and foreign patents, // maskwork rights, copyrights and other intellectual property laws...; eeleader FPGA/CPLD

[FPGA Design Problem] Three signal edges in the sensitivity list in Verilog: Data is sent when the rising edge of clock clk and signal A is high at the same time, but signal A has a fixed cycle (maintaining the high of 8 clocks), but when the rising edge of clock clk happens, ...; eeleader FPGA/CPLD

Newbie's question: What's wrong with the Baudrate calculation of my P89V51RD2?: Crystal: 32MHz Use timer2 as Baudrate Set TMOD = 0x21; // Use mode3 According to the formula Baud rate = fosc / (16 × (65536(RCAP2H, RCAP2L))) ---------------------------------------------------------...; liluo44 51mcu

I have used 430 to make DS18B20. Please help me modify the program.: Anyone who has used 430 to work on DS18B20, please help me modify the program. Below is the main function and the main parts of 18B20. Do you have any other questions? void main() { WDTCTL = WDTPW + W...; nwx8899 Microcontroller MCU

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