PTN3392
2-lane DisplayPort to VGA adapter IC
Rev. 4 — 8 October 2012
Product data sheet
1. General description
The PTN3392 is a DisplayPort to VGA adapter IC designed to connect a DisplayPort
source to a VGA sink. The PTN3392 integrates a DisplayPort receiver and a high-speed
triple video digital-to-analog converter that supports display resolutions from VGA to
WUXGA (see
Table 4).
The PTN3392 supports either one or two DisplayPort v1.1a lanes
operating at either 2.7 Gbit/s or 1.62 Gbit/s per lane. The PTN3392 has ‘Flash-over-AUX’
capability enabling simple firmware upgradability in the field.
The PTN3392 supports I
2
C-bus over AUX per
DisplayPort v1.1a specification
(Ref.
1),
and bridges the VESA DDC channel to the DisplayPort Interface.
The PTN3392 is designed for single supply and minimizes application costs. It can be
powered directly from the DisplayPort source side 3.3 V supply without a need for
additional core voltage regulator. The VGA output is powered down when there is no valid
DisplayPort source data being transmitted. The PTN3392 also aids in monitor detection
by performing load sensing and reporting sink connection status to the source.
2. Features and benefits
2.1 VESA compliant DisplayPort v1.1a converter
Main Link: 1-lane and 2-lane modes supported
HBR (High Bit Rate) at 2.7 Gbit/s per lane
RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane
BER (Bit Error Rate) better than 10
9
Down-spreading SSC (Spread Spectrum Clocking) supported
1 MHz AUX channel
Supports native AUX CH syntax
Supports I
2
C-bus over AUX CH syntax
Hot Plug Detect (HPD) signal to the source
Cost-effective design optimized for VGA application
2.2 DDC channel output
Supports 100 kbit/s I
2
C-bus speed, declared in DPCD register
Support of I
2
C-bus speed control by DisplayPort source via DPCD registers,
facilitating use of longer VGA cables
I
2
C Over Aux feature facilitates full support of MCCS, DDC-CI, and DDC protocols
(see
Ref. 2)
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
2.3 Analog video output
VSIS 1.2 compliance (Ref.
3)
for all supported video output modes
Analog RGB current-source outputs
VSYNC and HSYNC outputs
Pixel clock up to 240 MHz
Triple 8-bit Digital-to-Analog Converter (DAC)
Direct drive of double terminated 75
load with standard 700 mV (peak-to-peak)
signals
2.4 General features
Supports ‘Flash-over-AUX’ field upgradability
Monitor presence detection. Connection/disconnection reported via HPD IRQ and
DPCD update.
All display resolutions from VGA to WUXGA are supported
1
, including e.g.:
WUXGA: 6 bits, 1920
1200, 60 Hz, 193 MHz pixel clock rate
WUXGA: 1920
1200, 60 Hz, reduced blanking, 154 MHz pixel clock rate
UXGA: 1600
1200, 60 Hz, 162 MHz pixel clock rate
SXGA: 1280
1024, 60 Hz, 108 MHz pixel clock rate
XGA: 1024
768, 60 Hz, 65 MHz pixel clock rate
SVGA: 800
600, 60 Hz, 40 MHz pixel clock rate
VGA: 640
480, 60 Hz, 25 MHz pixel clock rate
Any resolution and refresh rates are supported up to 8 bit color
Bits per color (bpc) supported
1
6, 8 bits supported
10, 12, 16 bits supported by truncation to 8 MSBs
All VGA colorimetry formats (RGB) supported
Power modes
Active-mode power consumption:
~600 mW at UXGA / 162 MHz pixel clock
~500 mW at SXGA / 108 MHz pixel clock
~40 mW at Low-power mode or before link training started
On-board crystal oscillator for use with external 27 MHz crystal
ESD protection
7 kV ESD HBM JEDEC
8 kV ESD HBM IEC 61000-4-2 (Ref.
4)
3.3 V
10 % power supply
Commercial temperature range: 0
C
to 85
C
48-pin HVQFN, 7 mm
7 mm
0.85 mm (nominal); 0.5 mm pitch; lead-free package
1.
Except for color depth beyond 8 bits, display resolutions and refresh rates are only limited to those which a standard 2-lane
DisplayPort configuration is able to support.
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
PTN3392
Product data sheet
Rev. 4 — 8 October 2012
2 of 30
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
3. Applications
Dongle PC accessory
Dongle connected to PC DisplayPort output and connected to RGB monitor via
VGA cable
PTN3392 is powered by the DP_PWR pin on the DisplayPort connector
Desktop and notebook computers
Notebook docking stations
4. Ordering information
Table 1.
Ordering information
Topside mark
PTN3392BS
PTN3392BS
Package
Name
PTN3392BS
[1]
PTN3392BS/FX
[2]
HVQFN48
HVQFN48
Description
plastic thermal enhanced very thin quad flat package;
no leads; 48 terminals; 7
7
0.85 mm
plastic thermal enhanced very thin quad flat package;
no leads; 48 terminals; 7
7
0.85 mm
Version
SOT619-1
SOT619-1
Type number
[1]
[2]
PTN3392BS uses latest firmware version.
PTN3392BS/FX uses specific firmware version (‘X’ = 1, 2, 3, etc., and changes according to firmware version).
5. Functional diagram
PTN3392
RX PHY
ANALOG
SUBSYSTEM
DIFF CDR,
RCV S2P
RX PHY DIGITAL
DE-SCRAM
ISOCHRONOUS LINK
R[7:0]
INTERFACE DE-SKEWING
G[7:0]
MAIN
STREAM
B[7:0]
H, V
sync
VIDEO DAC SUBSYSTEM
MONITOR
PRESENCE
DETECT
DAC
DAC
DAC
R
VGA
OUTPUT
G
B
HSYNC
VSYNC
10b/8b
lane 0
TIME
CONV.
TIMING RECOVERY
V
bias
DIFF CDR,
RCV S2P
DE-SCRAM
10b/8b
lane 1
DPCD
REGISTERS
CONTROL
FLASH
MCU
V
bias
RCV
MANCHESTER
CODEC
AUX
DRV
RX ACLI
RX DIGITAL SUBSYSTEM
002aae032
AUX COMMAND
LEVEL MODULE
I
2
C-BUS
MASTER
SCL
SDA
V
bias
Fig 1.
Functional diagram
PTN3392
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 8 October 2012
3 of 30
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
6. Pinning information
6.1 Pinning
38 LDOCAP_AUX
48 GNDA_DP1
45 GNDA_DP0
40 AUX_N
39 AUX_P
47 ML1_N
44 ML0_N
46 ML1_P
43 ML0_P
41 GNDA
terminal 1
index area
RESET_N
CLK_O
HPD
VDDA_DP
TCK
TDO
GND_IO
TMS
TRST_N
1
2
3
4
5
6
7
8
9
37 VDDA
36 S3
35 S2
34 S1
33 S0
32 VDDD
31 VDDD
30 LDOCAP_CORE
29 GNDD
28 GNDD
27 OSC_OUT
26 OSC_IN
25 RED
RED_N 24
002aae033
PTN3392BS
TDI 10
SCL 11
VDD_IO 12
SDA 13
VSYNC 14
HSYNC 15
BLU 16
VDD_DAC 17
VDD_DAC 18
BLU_N 19
GRN_N 20
GRN 21
RSET 22
GND_DAC 23
Transparent top view
Fig 2.
Pin configuration for HVQFN48
6.2 Pin description
Table 2.
Symbol
VDDD
VDDA
VDDA_DP
VDD_IO
VDD_DAC
GND_IO
[1]
GND_DAC
[1]
GNDA_DP0
[1]
GNDA_DP1
[1]
GNDA
[1]
GNDD
[1]
Pin description
Pin
32, 31
37
4
12
17, 18
7
23
45
48
41
28, 29
Type
power
power
power
power
power
power
power
power
power
power
power
Description
digital core 3.3 V supply
analog AUX, bias and PLL 3.3 V supply
voltage
analog 3.3 V supply for DisplayPort receiver
module
I/O 3.3 V supply voltage
analog 3.3 V supply for DAC
I/O supply ground
analog ground for DAC
analog ground for DisplayPort Lane0
analog ground for DisplayPort Lane1
analog AUX, bias and PLL supply ground
digital core supply ground
PTN3392
All information provided in this document is subject to legal disclaimers.
42 RRX
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 8 October 2012
4 of 30
NXP Semiconductors
PTN3392
2-lane DisplayPort to VGA adapter IC
Pin description
…continued
Pin
43
44
46
47
39
Type
self-biasing
differential input
self-biasing
differential input
self-biasing
differential input
self-biasing
differential input
self-biasing
differential
input/output
self-biasing
differential
input/output
3.3 V TTL
single-ended output
analog output
analog output
analog output
analog output
analog output
analog output
analog input/output
Description
DisplayPort main lane signal lane 0, positive
DisplayPort main lane signal lane 0, negative
DisplayPort main lane signal lane 1, positive
DisplayPort main lane signal lane 1, negative
DisplayPort auxiliary channel signal, positive
Table 2.
Symbol
DisplayPort
ML0_P
ML0_N
ML1_P
ML1_N
AUX_P
AUX_N
40
DisplayPort auxiliary channel signal, negative
HPD
3
Hot-plug detect
RGB DAC outputs
BLU
BLU_N
GRN
GRN_N
RED
RED_N
RSET
16
19
21
20
25
24
22
‘blue’ current analog output
‘blue’ current complementary analog output
‘green’ current analog output
‘green’ current complementary analog output
‘red’ current analog output
‘red’ current complementary analog output
DAC full-scale current control resistor.
Pull down to ground by an external
1.2 k
1 % resistor.
5 V sink-side DDC clock I/O. Pulled up by
1.2 k external resistor to 5 V.
5 V sink-side DDC data I/O. Pulled up by
1.2 k external resistor to 5 V.
horizontal sync signal to monitor; serial
resistance of 36
is recommended.
vertical sync signal to monitor; serial
resistance of 36
is recommended.
JTAG clock input
JTAG data output
JTAG mode select input
JTAG reset (active LOW) input
JTAG data input
DDC
SCL
SDA
11
13
single-ended 5 V
open-drain DDC I/O
single-ended 5 V
open-drain DDC I/O
single-ended 3.3 V
TTL output
single-ended 3.3 V
TTL output
input
output
input
input
input
Monitor-side sync
HSYNC
VSYNC
JTAG
TCK
TDO
TMS
TRST_N
TDI
5
6
8
9
10
15
14
PTN3392
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 8 October 2012
5 of 30
京公网安备 11010802033920号
EEWORLD
