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P4C187L-35CI

Description
Standard SRAM, 64KX1, 35ns, CMOS, CDIP22, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-22
Categorystorage    storage   
File Size978KB,12 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C187L-35CI Overview

Standard SRAM, 64KX1, 35ns, CMOS, CDIP22, 0.300 INCH, SIDE BRAZED, CERAMIC, DIP-22

P4C187L-35CI Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPyramid Semiconductor Corporation
Parts packaging codeDIP
package instruction0.300 INCH, SIDE BRAZED, CERAMIC, DIP-22
Contacts22
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time35 ns
JESD-30 codeR-CDIP-T22
JESD-609 codee0
length29.337 mm
memory density65536 bit
Memory IC TypeSTANDARD SRAM
memory width1
Number of functions1
Number of terminals22
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize64KX1
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
P4C187/P4C187L
ULTRA HIGH SPEED 64K x 1
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35/45 ns (Commercial)
– 12/15/20/25/35 /45 ns (Industrial)
– 15/20/25/35/45/55/70/85 ns (Military)
Low Power Operation
Single 5V±10% Power Supply
Data Retention with 2.0V Supply (P4C187L)
Separate Data I/O
Three-State Output
TTL Compatible Output
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 22-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 22-Pin 290x490 mil LCC
– 28-Pin 350x550 mil LCC
DESCRIPTIOn
The P4C187/P4C187L are 65, 536-bit ultra high speed static
RAMs organized as 64K x 1. The CMOS memories require
no clocks or refreshing and have equal access and cycle
times. The RAMs operate from a single 5V ± 10% toler-
ance power supply. Data integrity is maintained for supply
voltages down to 2.0V for the Low Power version, typically
drawing 10µA.
Access times as fast as 10 nanoseconds are available,
greatly enhancing system speeds. CMOS reduces power
consumption to a low 743mW active, 193/83mW standby
for TTL/CMOS inputs and only 5.5 mW standby for the
P4C187L.
The P4C187/P4C187L are available in 22-pin 300 mil DIP,
24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages pro-
viding excellent board level densities.
FUnCTIOnAL BLOCk DIAgRAM
PIn COnFIgURATIOnS
DIP (P3, D3, C3)
SOJ (J4)
LCC configurations at end of datasheet
Document #
SRAM111
REV D
Revised October 2013
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