Features
H
12.4SPECint95,8.4SPECfp95 @266Mhz (750P)
w/1MB L2 @133Mhz
H
13.5SPECint95, 9SPECfp95 @300Mhz (740P)
H
488 MIPS @ 266Mhz
H
Selectable bus clock (11 CPU bus dividers up to 8x)
H
P
D
typical 4,2W @ 333Mhz, full operating conditions.
H
Nap, doze and sleep modes for power savings
H
Superscalar (3 instructions per clock cycle)
H
4G-Byte direct addressing range.
H
64-bit data and 32-bit address bus interface.
H
32KB instruction and data cache.
H
Six independent execution units and two register files.
H
Write-back and write-through operations.
H
f
int
max = 333Mhz
H
f
bus
max = 100Mhz
H
Compatible CMOS input / TTL output
PCX750P/740P
PowerPC750P/740P
RISC MICROPRO-
CESSOR
Family
Pid8t-750P/740P
Specification
Preliminary
Description
The PCX750P and PCX740P microprocessor (after named 750P/740P) are low-power imple-
mentations of the PowerPC Reduced Instruction Set Computer (RISC) architecture.
The 750P/740P microprocessors designs are superscalar, capable of issuing three instructions
per clock cycle into six independent execution units
The 740P/750P microprocessors uses a 1,9/3,3-volts CMOS process technology and maintains
full interface compatibility with TTL devices.
The 750P/740P provides four software controlable power-saving modes and a thermal assist
unit management.
The 750P/740P microprocessors have separate 32-Kbyte, physically-addressed instruction
and data caches and differ only in that the 750P features a dedicated L2 cache interface with
on-chip L2 tags.
Both are software and bus-compatible with the PowerPC603 and PowerPC604 families, and are
fully JTAG compliant.
The 740P microprocessor is pin compatible with the TSPC603e family.
G suffix
GS suffix
CBGA255 and CBGA360
Ceramic Ball Grid Array
CI-CGA255 and CI-CGA360
Ceramic Ball Grid Array
with Solder Column Interposer (SCI)
Screening
This product is manufactured in full compliance with :
H
CBGA upscreenings based upon ATMEL-Grenoble standards
H
Full military temperature range (Tc=-55
o
C,+125
o
C)
industrial temperature range (Tc=-40
o
C,+110
o
C)
H
CI-CGA versions of 740P and 750P (TBC)
August 2000
1/42
SUMMARY
A. GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . 3
1. SIMPLIFIED BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . 3
1.1. General parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. PIN ASSIGNEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1. 740P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2. 750P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3. PINOUT LISTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.1. Pinout listing for the 740P, 255 CBGA and
CI-CGA packages. . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.2. Pinout listing for the 750P, 360 CBGA package. . 10
2.4. Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.1.1. Mechanical Dimensions of the 740P CBGA
package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1.2. Mechanical Dimensions of the 740P CI-CGA
package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2. Parameters for the 750P . . . . . . . . . . . . . . . . . . . . . 35
7.2.1. Mechanical Dimensions of the 750P CBGA
package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.2. Mechanical Dimensions of the 750P CI-CGA
package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8. CLOCK RELATIONSHIPS CHOICE . . . . . . . . . . . . . . . 36
9. SYSTEM DESIGN INFORMATION . . . . . . . . . . . . . . . . .
9.1. PLL Power Supply Filtering . . . . . . . . . . . . . . . . . .
9.2. Decoupling Recommendations . . . . . . . . . . . . . .
9.3. Connection Recommendations . . . . . . . . . . . . . .
9.4. Output Buffer DC Impedance . . . . . . . . . . . . . . . .
9.5. Pull-up Resistor Requirements . . . . . . . . . . . . . .
39
39
39
39
39
40
B. DETAILED SPECIFICATION . . . . . . . . . . . . . . . . 14
1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . . . . . . 14
3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2. Design and construction . . . . . . . . . . . . . . . . . . . .
3.2.1. Terminal connections . . . . . . . . . . . . . . . . . . . . . . .
3.3. Absolute maximum rating . . . . . . . . . . . . . . . . . . .
3.4. Recommendated operating conditions . . . . . . .
3.5. Thermal characteristics . . . . . . . . . . . . . . . . . . . . .
3.5.1. Package characteristics . . . . . . . . . . . . . . . . . . . . .
3.5.2. Thermal management assistance . . . . . . . . . . . . .
3.5.3. Thermal Management Information . . . . . . . . . . . .
3.6. Power consideration . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1. Power management . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2. Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . .
4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . .
4.1. Static characteristics . . . . . . . . . . . . . . . . . . . . . . .
4.2. Dynamic characteristics . . . . . . . . . . . . . . . . . . . . .
4.2.1. Clock AC Specifications . . . . . . . . . . . . . . . . . . . . .
4.2.2. 60x Bus Input AC Specifications . . . . . . . . . . . . . .
4.2.3. 60x Bus Output AC Specifications . . . . . . . . . . . .
4.2.4. L2 Clock AC Specifications . . . . . . . . . . . . . . . . . .
4.2.5. L2 Bus Input AC Specifications . . . . . . . . . . . . . . .
4.2.6. L2 Bus Output AC Specifications . . . . . . . . . . . . .
4.2.7. IEEE 1149.1 AC Timing Specifications . . . . . . . . .
14
14
14
14
14
15
16
16
16
17
19
19
20
21
21
21
22
23
24
26
29
29
30
10. DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
11. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . 42
5. PREPARATION FOR DELIVERY . . . . . . . . . . . . . . . . . . 32
5.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2. Certificate of compliance . . . . . . . . . . . . . . . . . . . . 32
6. HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7. PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . 33
7.1. Parameters for the 740P . . . . . . . . . . . . . . . . . . . . . 33
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750P/740P
750P/740P
A. GENERAL DESCRIPTION
1. SIMPLIFIED BLOCK DIAGRAM
The 750P is targeted for low power systems and supports the following power management features-doze, nap, sleep, and dynamic
power management. The 750P consists of a processor core and an internal L2 Tag combined with a dedicated L2 cache interface and
a 60x bus.
Instruction Fetch
Branch Unit
Completion
Control Unit
32K ICache
System Unit
Dispatch
BHT/BTIC
GPRs
FXU1
FXU2
Rename
Buffers
LSU
FPRs
Rename
Buffers
FPU
32K DCache
L2 Tags
L2 Cache
BIU
60x BIU
Figure 1. PCX750P Block Diagram
1.1. General parameters
The general parameters of the 750P/740P are the following :
Technology
0.18
mm
CMOS, five-layer metal
Die size
7.56 mm x 8.79 mm (67 mm
2
)
Transistor count
6.35 million
Logic design Fully-static
Packages
740P: Surface mount 255 ceramic ball grid array (CBGA) and column interposer ceramic grid array CI-CGA without
L2 interface
750P: Surface mount 360 ceramic ball grid array (CBGA) and column interposer ceramic grid array CI-CGA with L2
interface
Core power supply
1.9V
"100
mV
I/O power supply
3.3V
"5%
V dc
1.2. Features
Except L2 cache interface that is not supported by the PowerPC version, the major features implemented in the 750P architecture are
as follow:
3/42
•
Level 2 (L2) cache interface (not implemented on TSPC740P)
-
-
-
-
-
-
Internal L2 cache controller and 4K-entry tags; external data SRAMs
256K, 512K, and 1 Mbyte 2-way set associative L2 cache support
Copy-back or write-through data cache (on a page basis, or for all L2)
64-byte (256K/512K) and 128-byte (1-Mbyte) sectored line size
Supports flow-through (reg-buf) synchronous burst SRAMs, pipelined (reg-reg) synchronous burst SRAMs, and
pipelined (reg-reg) late-write synchronous burst SRAMs
Core-to-L2 frequency divisors of
÷1, ÷1.5, ÷2, ÷2.5,
and
÷3
supported
•
Branch processing unit
-
-
-
-
-
Four instructions fetched per clock
One branch processed per cycle (plus resolving 2 speculations)
Up to 1 speculative stream in execution, 1 additional speculative stream in fetch
512-entry branch history table (BHT) for dynamic prediction
64-entry, 4-way set associative branch target instruction cache (BTIC) to minimize branch delay slots
•
Dispatch unit
-
-
-
Full hardware detection of dependencies (resolved in the execution units)
Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2,
or floating-point)
Serialization control (predispatch, postdispatch, execution serialization)
•
Load/store unit
-
-
-
-
-
-
-
-
-
-
-
One cycle load or store cache access (byte, half-word, word, double-word)
Effective address generation
Hits under misses (one outstanding miss)
Single-cycle misaligned access within double word boundary
Alignment, zero padding, sign extend for integer register file
Floating-point internal format conversion (alignment, normalization)
Sequencing for load/store multiples and string operations
Store gathering
Cache and TLB instructions
Big- and little-endian byte addressing supported
Misaligned little-endian support in hardware
•
Fixed-point units
-
-
-
-
-
Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
Fixed-point unit 2 (FXU2)—shift, rotate, arithmetic, logical
Single-cycle arithmetic, shift, rotate, logical
Multiply and divide support (multi-cycle)
Early out multiply
4/42
750P/740P
750P/740P
•
Bus interface
-
-
-
-
Compatible with 60x processor interface
32-bit address bus
64-bit data bus
Bus-to-core frequency multipliers of 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x , 8x supported
•
Decode
-
-
-
Register file access
Forwarding control
Partial instruction decode
•
Floating-point unit
-
-
-
-
-
-
-
Support for IEEE-754 standard single- and double-precision floating-point arithmetic
3 cycle latency, 1 cycle throughput, single-precision multiply-add
3 cycle latency, 1 cycle throughput, double-precision add
4 cycle latency, 2 cycle throughput, double-precision multiply-add
Hardware support for divide
Hardware support for denormalized numbers
Time deterministic non-IEEE mode
•
System unit
-
-
Executes CR logical instructions and miscellaneous system instructions
Special register transfer instructions
•
Cache structure
-
-
-
-
-
-
-
-
32K, 32-byte line, 8-way set associative instruction cache
32K, 32-byte line, 8-way set associative data cache
Single-cycle cache access
Pseudo-LRU replacement
Copy-back or write-through data cache (on a page per page basis)
Supports all PowerPC memory coherency modes
Non-blocking instruction and data cache (one outstanding miss under hits)
No snooping of instruction cache
•
Memory management unit
-
-
-
-
-
-
128 entry, 2-way set associative instruction TLB
128 entry, 2-way set associative data TLB
Hardware reload for TLBs
4 instruction BATs and 4 data BATs
Virtual memory support for up to 4 exabytes (2
52
) of virtual memory
Real memory support for up to 4 gigabytes (2
32
) of physical memory
•
Testability
-
-
LSSD scan design
JTAG interface
5/42
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