PC7447AVGH1000NB datasheet, PDF

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PC7447AVGH1000NB: DescriptionRISC Microprocessor, 32-Bit, 1000MHz, CMOS, CBGA360, 25 X 25 MM, 3.24 MM HEIGHT, 1.27 MM PITCH, CERAMIC, HITCE, BGA-360; CategoryThe embedded processor and controller Microcontrollers and processors; File Size776KB，51 Pages; Manufacturere2v technologies

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PC7447AVGH1000NB Overview

RISC Microprocessor, 32-Bit, 1000MHz, CMOS, CBGA360, 25 X 25 MM, 3.24 MM HEIGHT, 1.27 MM PITCH, CERAMIC, HITCE, BGA-360

PC7447AVGH1000NB Parametric

Parameter Name	Attribute value
Maker	e2v technologies
Parts packaging code	BGA
package instruction	BGA,
Contacts	360
Reach Compliance Code	compliant
ECCN code	3A001.A.3
Address bus width	36
bit size	32
boundary scan	YES
maximum clock frequency	167 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CBGA-B360
length	25 mm
low power mode	YES
Number of terminals	360
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	3.2 mm
speed	1000 MHz
Maximum supply voltage	1.15 V
Minimum supply voltage	1.05 V
Nominal supply voltage	1.1 V
surface mount	YES
technology	CMOS
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	25 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

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PC7447A

PowerPC 7447A RISC Microprocessor

Datasheet

Features

•

3000 Dhrystone 2.1 MIPS at 1.3 GHz

Selectable Bus Clock (30 CPU Bus Dividers up to 28x)

Selectable MPx/60x Interface Voltage (1.8V, 2.5V)

Typically 18W at 1.33 GHz at V

= 1.3V; 8.0W at 1 GHz at V

= 1.1V

Full Operating Conditions

Nap, Doze and Sleep Power Saving Modes

Superscalar (Four Instructions Fetched Per Clock Cycle)

4 GB Direct Addressing Range

Virtual Memory: 4 Hexabytes (2

)

64-bit Data and 36-bit Address Bus Interface

Integrated L1: 32 KB Instruction and 32 KB Data Cache

Integrated L2: 512 KB

11 Independent Execution Units and three Register Files

Write-back and Write-through Operations

INT

Max = 1.167 MHz

BUS

Max = 133 MHz/166 MHz

Description

The PC7447A host processor is a high-performance, low-power, 32-bit implementations of the PowerPC

Reduced

Instruction Set Computer (RISC) architecture combined with a full 128-bit implementation of Freescale’s AltiVec

technology.

This microprocessor is ideal for leading-edge embedded computing and signal processing applications. The PC7447A fea-

tures 512 KB of on-chip L2 cache. The PC7447A microprocessor has no backside L3 cache, allowing for a smaller

package designed as a pin-for-pin replacement for the PC7447 microprocessor. This device benefits from a silicon-on-

insulator (SOI) CMOS process technology, engineered to help deliver tremendous power savings without sacrificing speed.

A low-power version of the PC7447A microprocessor is also available.

Figure 1-1 on page 2

shows a block diagram of the PC7447A. The core is a high-performance superscalar design support-

ing a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX

bus protocol and a subset of the 60x bus protocol to the main memory and other system resources.

Note that the PC7447A is a footprint-compatible, drop-in replacement in a PC7447 application if the core power supply is

1.3V.

Screening

•

Full Military Temperature Range (T

= -55°C, +125°C)

•

Industrial Temperature Range (T

= -40°C, +110°C)

Visit our website: www.e2v.com

for the latest version of the datasheet

e2v semiconductors SAS 2007

0833E–HIREL–01/07

PC7447A

2. Features

This section summarizes features of the PC7447A implementation of the PowerPC architecture.

Major features of the PC7447A are as follows:

• High-performance, superscalar microprocessor

– Up to four instructions can be fetched from the instruction cache at a time

– Up to 12 instructions can be in the instruction queue (IQ)

– Up to 16 instructions can be at some stage of execution simultaneously

– Single-cycle execution for most instructions

– One instruction per clock cycle throughput for most instructions

– Seven-stage pipeline control

• Eleven independent execution units and three register files

– Branch processing unit (BPU) features static and dynamic branch prediction

128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache

of branch instructions that have been encountered in branch/loop code sequences. If a

target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it

can be made available from the instruction cache. Typically, a fetch that hits the BTIC

provides the first four instructions in the target stream.

2048-entry branch history table (BHT) with two bits per entry for four levels of prediction: not

taken, strongly not taken, taken, and strongly taken

Up to three outstanding speculative branches

Branch instructions that do not update the count register (CTR) or link register (LR) are often

removed from the instruction stream

Eight-entry link register stack to predict the target address of Branch Conditional to Link

– Four integer units (IUs) that share 32 GPRs for integer operands

Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except

multiply, divide, and move to/from special-purpose register instructions.

IU2 executes miscellaneous instructions including the CR logical operations, integer

multiplication and division instructions, and move to/from special-purpose register

instructions.

– Five-stage FPU and a 32-entry FPR file

Fully IEEE

754-1985-compliant FPU for both single- and double-precision operations

Supports non-IEEE mode for time-critical operations

Hardware support for denormalized number

0833E–HIREL–01/07

e2v semiconductors SAS 2007

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