Z8S18020VEG datasheet, PDF - EEWORLD Datasheet

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Z8S18020VEG: DescriptionMicroprocessor, 8-Bit, 20MHz, CMOS, PQCC68, PLASTIC, LCC-68; CategoryThe embedded processor and controller Microcontrollers and processors; File Size910KB，71 Pages; ManufacturerIXYS; Environmental Compliance

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Z8S18020VEG Overview

Microprocessor, 8-Bit, 20MHz, CMOS, PQCC68, PLASTIC, LCC-68

Z8S18020VEG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IXYS
Parts packaging code	LCC
package instruction	PLASTIC, LCC-68
Contacts	68
Reach Compliance Code	compliant
ECCN code	3A001.A.2.C
Other features	ALSO OPERATES AT 3.3V SUPPLY
Address bus width	20
bit size	8
boundary scan	NO
maximum clock frequency	20 MHz
External data bus width	8
Format	FIXED POINT
Integrated cache	NO
JESD-30 code	S-PQCC-J68
JESD-609 code	e3
length	24.2316 mm
low power mode	YES
Number of terminals	68
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	4.57 mm
speed	20 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	MATTE TIN
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	24.2316 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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Code Compatible with ZiLOG Z80

CPU

Extended Instructions

Two Chain-Linked DMA Channels

Low Power-Down Modes

On-Chip Interrupt Controllers

Three On-Chip Wait-State Generators

On-Chip Oscillator/Generator

Expanded MMU Addressing (Up to 1 MB)

Clocked Serial I/O Port

Two 16-Bit Counter/Timers

Two Enhanced UARTs (up to 512 Kbps)

Clock Speeds: 10, 20, 33 MHz

Operating Range: 5V (3.3V@ 20 MHz)

Operating Temperature Range: 0°C to +70°C

–40°C to +85°C Extended Temperature Range

Three Packaging Styles

– 68-Pin PLCC

– 64-Pin DIP

– 80-Pin QFP

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The enhanced Z8S180/Z8L180

™

significantly improves on

previous Z80180 models, while still providing full back-

ward compatibility with existing ZiLOG Z80 devices. The

Z8S180/Z8L180 now offers faster execution speeds, pow-

er-saving modes, and EMI noise reduction.

This enhanced Z180

™

design also incorporates additional

feature enhancements to the ASCIs, DMAs, and

56#0&$;

mode power consumption. With the addition of ESCC-like

Baud Rate Generators (BRGs), the two ASCIs offer the flex-

ibility and capability to transfer data asynchronously at rates

of up to 512 Kbps. In addition, the ASCI receiver features

a 4-byte first in/first out (FIFO) buffer which reduces the

likelihood of overrun errors. The DMAs have been modified

to allow for chain-linking of the two DMA channels when

set to take their DMA requests from the same peripherals

device. This feature allows for nonstop DMA operation be-

tween the two DMA channels.

Not only does the Z8S180/Z8L180 consume less power dur-

ing normal operations than the previous model, it offers

three modes intended to further reduce power consumption.

Power consumption during

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Mode is reduced to

µA

by stopping the external oscillators and internal

clock. The

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mode reduces power by placing the CPU

into a stopped state, consuming less current while the on-

chip I/O devices still operate. The

5;56'/ 5612

mode

places both the CPU and the on-chip peripherals into a

stopped mode, reducing power consumption even further.

A new clock-doubler feature in the Z8S180/Z8L180 allows

the internal clock speed to be twice the external clock speed.

As a result, system cost is reduced by allowing the use of

lower-cost, lower-frequency crystals.

The Enhanced Z180 is housed in 80-pin QFP, 68-pin PLCC,

and 64-pin DIP packages.

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All Signals with an overline are active Low. For exam-

ple: B/W, in which WORD is active Low; or B/W, in

which BYTE is active Low.

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