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PIC32MZ1024EFG100250I/PT

Description
Microcontroller, 32-Bit, FLASH, 252MHz, CMOS, PQFP100
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size11MB,754 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric View All

PIC32MZ1024EFG100250I/PT Overview

Microcontroller, 32-Bit, FLASH, 252MHz, CMOS, PQFP100

PIC32MZ1024EFG100250I/PT Parametric

Parameter NameAttribute value
MakerMicrochip
package instructionTFQFP,
Reach Compliance Codecompliant
Has ADCYES
Address bus width
bit size32
maximum clock frequency64 MHz
DAC channelNO
DMA channelYES
External data bus width
JESD-30 codeS-PQFP-G100
length12 mm
Number of I/O lines78
Number of terminals100
On-chip program ROM width8
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
PWM channelYES
Package body materialPLASTIC/EPOXY
encapsulated codeTFQFP
Package shapeSQUARE
Package formFLATPACK, THIN PROFILE, FINE PITCH
ROM programmabilityFLASH
Filter levelTS 16949
Maximum seat height1.2 mm
speed252 MHz
Maximum supply voltage3.6 V
Minimum supply voltage2.1 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.4 mm
Terminal locationQUAD
width12 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER
PIC32MZ Embedded Connectivity
with Floating Point Unit (EF) Family
32-bit MCUs (up to 2 MB Live-Update Flash and 512 KB SRAM) with FPU,
Audio and Graphics Interfaces, HS USB, Ethernet, and Advanced Analog
Operating Conditions
• 2.1V to 3.6V, -40ºC to +85ºC, DC to 252 MHz
• 2.1V to 3.6V, -40ºC to +125ºC, DC to 180 MHz
Advanced Analog Features
• 12-bit ADC module:
- 18 Msps with up to six Sample and Hold (S&H) circuits
(five dedicated and one shared)
- Up to 48 analog inputs
- Can operate during Sleep and Idle modes
- Multiple trigger sources
- Six Digital Comparators and six Digital Filters
• Two comparators with 32 programmable voltage
references
• Temperature sensor with ±2ºC accuracy
Core: 252 MHz (up to 415 DMIPS) M-Class
16 KB I-Cache, 4 KB D-Cache
FPU for 32-bit and 64-bit floating point math
MMU for optimum embedded OS execution
microMIPS™ mode for up to 35% smaller code size
DSP-enhanced core:
- Four 64-bit accumulators
- Single-cycle MAC, saturating, and fractional math
- IEEE 754-compliant
• Code-efficient (C and Assembly) architecture
Communication Interfaces
• Two CAN modules (with dedicated DMA channels):
- 2.0B Active with DeviceNet™ addressing support
• Six UART modules (25 Mbps):
- Supports up to LIN 2.1 and IrDA
®
protocols
• Six 4-wire SPI modules (up to 50 MHz)
• SQI configurable as an additional SPI module (50 MHz)
• Five I
2
C modules (up to 1 Mbaud) with SMBus support
• Parallel Master Port (PMP)
• Peripheral Pin Select (PPS) to enable function remap
Clock Management
• Programmable PLLs and oscillator clock sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timers (WDT) and Deadman
Timer (DMT)
• Fast wake-up and start-up
Power Management
• Low-power modes (Sleep and Idle)
• Integrated Power-on Reset (POR) and Brown-out Reset
(BOR)
Timers/Output Compare/Input Capture
Nine 16-bit or up to four 32-bit timers/counters
Nine Output Compare (OC) modules
Nine Input Capture (IC) modules
Real-Time Clock and Calendar (RTCC) module
Memory Interfaces
• 50 MHz External Bus Interface (EBI)
• 50 MHz Serial Quad Interface (SQI)
Input/Output
• 5V-tolerant pins with up to 32 mA source/sink
• Selectable open drain, pull-ups, pull-downs, and slew rate
controls
• External interrupts on all I/O pins
• PPS to enable function remap
Audio and Graphics Interfaces
Graphics interfaces: EBI or PMP
Audio data communication: I
2
S, LJ, and RJ
Audio control interfaces: SPI and I
2
C
Audio master clock: Fractional clock frequencies with USB
synchronization
Qualification and Class B Support
• AEC-Q100 REVH (Grade 1 -40ºC to +125ºC)
• Class B Safety Library, IEC 60730 (planned)
• Back-up internal oscillator
High-Speed (HS) Communication Interfaces
(with Dedicated DMA)
• USB 2.0-compliant Hi-Speed On-The-Go (OTG) controller
• 10/100 Mbps Ethernet MAC with MII and RMII interface
Debugger Development Support
In-circuit and in-application programming
4-wire MIPS
®
Enhanced JTAG interface
Unlimited software and 12 complex breakpoints
IEEE 1149.2-compatible (JTAG) boundary scan
Non-intrusive hardware-based instruction trace
C/C++ compiler with native DSP/fractional and FPU support
MPLAB
®
Harmony Integrated Software Framework
TCP/IP, USB, Graphics, and mTouch™ middleware
MFi, Android™, and Bluetooth
®
audio frameworks
RTOS Kernels: Express Logic ThreadX, FreeRTOS™,
OPENRTOS
®
, Micriµm
®
µC/OS™, and SEGGER embOS
®
TFBGA
VTLA
LQFP
Security Features
• Crypto Engine with RNG for data encryption/decryption and
authentication (AES, 3DES, SHA, MD5, and HMAC)
• Advanced memory protection:
- Peripheral and memory region access control
Software and Tools Support
Direct Memory Access (DMA)
• Eight channels with automatic data size detection
• Programmable Cyclic Redundancy Check (CRC)
Packages
Type
QFN
TQFP
Pin Count
64
64
100
144
100
144
124
144
I/O Pins (up to)
53
53
78
120
78
120
98
120
Contact/Lead Pitch
0.50 mm
0.50 mm
0.40 mm
0.50 mm
0.40 mm
0.65 mm
0.50 mm
0.50 mm
0.50 mm
Dimensions
9x9x0.9 mm 10x10x1 mm 12x12x1 mm 14x14x1 mm 16x16x1 mm 7x7x1.2 mm 7x7x1.2 mm 9x9x0.9 mm 20x20x1.40 mm
2015-2019 Microchip Technology Inc.
DS60001320F-page 1
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